MB85RS4MT

DS501-00053-3v1-E

9



FSTRD

The FSTRD command reads FeRAM memory cell array data. Arbitrary 24 bits address and op-code of

FSTRD are input to SI followed by 8 bits dummy. The 5-bit upper address bit is invalid. Then, 8-cycle clock

is input to SCK. SO is output synchronously to the falling edge of SCK. While reading, the SI value is invalid.

When CS is risen, the FSTRD command is completed, but keeps on reading with automatic address incre-

ment which is enabled by continuously sending clocks to SCK in unit of 8 cycles before CS rising. When it

reaches the most significant address, it rolls over to the starting address, and reading cycle keeps on infinitely.



RDID

The RDID command reads fixed Device ID. After performing RDID op-code to SI, 32-cycle clock is input to

SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. The output

is in order of Manufacturer ID (8bit)/Continuation code (8bit)/Product ID (1st Byte)/Product ID (2nd Byte).

In the RDID command, SO holds the output state of the last bit in 32-bit Device ID until CS is risen.

CS

SCK

SI

Invalid

MSB

LSB

MSB

Data Out LSB

High-Z

Invalid

45

0123

29 30

6 7 8 9 10 11 12 13 1415

46 47

31 32

38 39 40 41 42 43 44 45

00001011 X

6

16

210 X

XX

SO

7

X X X X 18 17

0

543

33

X

21

24-bit Address

8-bit Dummy

OP-CODE

SO

SCK

SI

CS

MSB

7

6

5

4

3

2

1

0

Data Out

Data Out

High-Z

LSB

11

10

9

8

33

32

31

39

38

37

36

35

34

Invalid

30

28

29

31

10011111

20

1

3

64

5

7

8

bit

7

6

5

4

3

2

1

0 Hex

Manufacturer ID

0

0

0

0

0

1

0

0

04H RAMXEED

Continuation code

0

1

1

1

1

1

1

1

7FH

Proprietary use

Density

Hex

Product ID (1st Byte)

0

1

0

0

1

0

0

1

49H Density: 01001B  4Mbit

Proprietary use

Hex

Product ID (2nd Byte)

0

0

0

0

0

0

1

1

03H