CDCLVC1310 datasheet(4/31 Pages) TI2

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CDCLVC1310

SCAS917E – JULY 2011 – REVISED JANUARY 2014

www.ti.com

PIN FUNCTIONS

I/O

TYPE

DESCRIPTION

NAME

NO(s)

4, 9, 15,

16, 21,

GND

PWR

Analog

Power-supply ground

25, 26,

IN_SEL0,

30, 29

Digital

Input-clock selection (pulldown of 150 k

Ω)

IN_SEL1

Digital

LVCMOS output enable (pulldown of 150 k

Ω)

Inverting differential primary reference input, internally biased to Vdd / 2 (pullup or

PRI_INN

Analog

pulldown of 150 k

Ω)

PRI_INP

Analog

Non-inverting differential or single-ended primary reference input (pulldown of 150 k

Ω)

Inverting differential secondary reference input, internally biased to Vdd / 2 (pullup or

SEC_INN

Analog

pulldown of 150 k

Ω)

SEC_INP

Analog

Non-inverting differential or single-ended secondary reference input (pulldown of 150 k

Ω)

VDD

PWR

Analog

Power-supply pins

2, 6, 19,

VDDO

PWR

Analog

I/O power-supply pins

XIN

Analog

Crystal-oscillator input or XTAL bypass mode

XOUT

Analog

Crystal-oscillator output

Analog

LVCMOS output 0

Analog

LVCMOS output 1

Analog

LVCMOS output 2

Analog

LVCMOS output 3

Analog

LVCMOS output 4

Analog

LVCMOS output 5

Analog

LVCMOS output 6

Analog

LVCMOS output 7

Analog

LVCMOS output 8

Analog

LVCMOS output 9

Table 1. Input Selection

IN_SEL1

IN_SEL0

INPUT CHOSEN

PRI_IN

SEC_IN

XTAL or overdrive(1)

XTAL bypass(2)

(1)

This mode is for XTAL input or overdrive of XTAL oscillator with

LVCMOS input. For characteristics; see LVCMOS OUTPUT

CHARACTERISTICS.

(2)

This mode is only XTAL bypass. For characteristics, see LVCMOS

OUTPUT CHARACTERISTICS.

Table 2. INPUT/OUTPUT OPERATION(1)

INPUT STATE

OUTPUT STATE

PRI_INx, SEC_INx open

Logic LOW

PRI_INP, SEC_INP = HIGH,

Logic HIGH

PRI_INN, SEC_INN = LOW

PRI_INP, SEC_INP = LOW,

Logic LOW

PRI_INN, SEC_INN = HIGH

(1)

Device must have switching edge to obtain output states.

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