Differential

LVCMOS

LVCMOS

LVCMOS

t

PD

t

SK

PRI_IN/SEC_IN

PRI_IN/SEC_IN (N)

PRI_IN/SEC_IN (P)

Yx

Yy

Yx

V

OUT

t

R

t

F

80%

20%

0V

LVC1310

output

VDDO

Z = 50

O

W

LVCMOS

input

10 pF

R

35

, 30

, 20

, 10

(V

= 3.3 V, 2.5 V, 1.8 V, 1.5 V)

S

DDO

»

W

W

W

W

CDCLVC1310

www.ti.com

SCAS917E – JULY 2011 – REVISED JANUARY 2014

APPLICATION INFORMATION

Typical Application Load

Figure 9. LVCMOS Output DC Configuration: Typical Application Load

Parameter Measurement Information

Figure 10. LVCMOS Output Voltage, and Rise and Fall Times

Figure 11. Differential and Single-Ended Output Skew and Propagation Delay

Crystal Oscillator Input

The crystal oscillator circuit is characterized with 18-pF parallel-resonant crystals. Choices of C1 and C2 were to

minimize the ppm error. Optional resistor ROPTIONAL limits the drive level of the oscillator circuit.

Copyright © 2011–2014, Texas Instruments Incorporated

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