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DP83867CSRGZR.B Datasheet(PDF) 64 Page - Texas Instruments |
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DP83867CSRGZR.B Datasheet(HTML) 64 Page - Texas Instruments |
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64 / 129 page  Table 7-27. Interrupt Status Register (ISR), Address 0x0013 (continued) BIT BIT NAME DEFAULT DESCRIPTION 5 SPEED_OPT_EVENT_INT 0, RO, LH, COR Speed Optimization Event Interrupt: 1 = Speed Optimization Event Interrupt is pending and is cleared by the current read. 0 = No Speed Optimization Event Interrupt is pending. 4 SLEEP_MODE_CHNG_INT 0, RO, LH, COR Sleep Mode Change Interrupt: 1 = Sleep Mode Change Interrupt is pending and is cleared by the current read. 0 = No Sleep Mode Change Interrupt is pending. 3 WOL_INT 0, RO, LH, COR Wake-on-LAN Interrupt: 1 = Wake-on-LAN Interrupt is pending. 0 = No Wake-on-LAN Interrupt is pending. 2 XGMII_ERR_INT 1 0, RO, LH, COR xGMII Error Interrupt: 1 = xGMII Error Interrupt is pending and is cleared by the current read. 0 = No xGMII Error Interrupt is pending. 1 POLARITY_CHNG_INT 0, RO, LH, COR Polarity Change Interrupt: 1 = Polarity Change interrupt is pending and is cleared by the current read. 0 = No Polarity Change interrupt is pending. 0 JABBER_INT 0, RO, LH, COR Jabber Interrupt: 1 = Jabber interrupt is pending and is cleared by the current read. 0 = No Jabber interrupt is pending. 1 xGMII: RGMII or SGMII DP83867CS, DP83867IS, DP83867E SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025 www.ti.com 64 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: DP83867CS DP83867IS DP83867E |
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