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DP83867CSRGZR.B Datasheet(PDF) 13 Page - Texas Instruments |
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DP83867CSRGZR.B Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 129 page  6.11 DP83867E Start of Frame Detection Timing Figure 6-7 PARAMETER TEST CONDITIONS MIN NOM MAX UNIT T1 Transmit SFD variation(1) (2) 1000Mb Master 0 0 ns 1000Mb Slave 0 0 ns 100Mb 0 8 ns T2 Receive SFD variation(1) (2) 1000Mb Master –4 4 ns 1000Mb Slave 0 0 ns 100Mb 0 0 ns (1) A larger variation can be seen on SFD pulses than the variation specified here. To achieve the determinism specification listed, see the Section 7.3.2.1 section for a method to compensate for variation in the SFD pulses. (2) Variation of SFD pulses occurs from link-up to link-up. Packet to packet variation is fixed using the estimation method in Section 7.3.2.1. 6.12 DP83867IS/CS Start of Frame Detection Timing Figure 6-8 PARAMETER TEST CONDITIONS MIN NOM MAX UNIT T1 Transmit SFD variation(1) (2) 1000Mb Master 0 0 ns 1000Mb Slave 0 0 ns 100Mb 0 16 ns T2 Receive SFD variation(1) (2) 1000Mb Master –8 8 ns 1000Mb Slave –8 8 ns 100Mb 0 0 ns (1) A larger variation can be seen on SFD pulses than the variation specified here. To achieve the determinism specification listed, see the Section 7.3.2.1 section for a method to compensate for variation in the SFD pulses. (2) Variation of SFD pulses occurs from link-up to link-up. Packet to packet variation is fixed using the estimation method in Section 7.3.2.1. 6.13 Timing Diagrams T1 T2 32 CLOCKS T3 OUTPUT INPUT VDD XI clock Hardware RESET_N MDC Latch-In of Hardware Configuration Pins Dual Function Pins Become Enabled As Outputs Figure 6-1. Power-Up Timing www.ti.com DP83867CS, DP83867IS, DP83867E SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: DP83867CS DP83867IS DP83867E |
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