Data Sheet

ADRF5702

THEORY OF OPERATION

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Rev. A | 23 of 27

The ADRF5702 incorporates a 8-bit fixed attenuator array that

offers an attenuation range of 31.875 dB with a 0.125 dB step size.

An integrated driver provides serial or parallel mode control of the

attenuator array.

The ADRF5702 has ten digital control inputs, D0 (LSB) to D7

(MSB), LE, and PS. To select the desired attenuation state in serial

or parallel mode, refer to Table 8 and Table 9. For timing diagrams,

see Figure 53, Figure 54, and Figure 55.

POWER SUPPLY

The ADRF5702 requires a positive supply voltage applied to the

VDD pin. The device does not support supply intermediate supply

voltage levels except the values listed in the Electrical Specifica-

tions section. Bypassing capacitors are recommended on the sup-

ply line to filter high frequency noise.

The power-up sequence follows:

1. Connect GND to ground.

2. Power up the VDD voltage.

3. Power up the digital control inputs. The order of the digital

control inputs is not important. However, powering the digital

control inputs before the VDD voltage supply can inadvertently

forward bias and damage the internal ESD structures. To avoid

this damage, use a series 1kΩ resistor to limit the current

flowing into the control pins in such cases.

4. Apply an RF input signal.

The power-down sequence is the reverse order of the power-up

sequence.

Power-Up State

The ADRF5702 has internal power-on reset circuitry that sets the

attenuator to the maximum attenuation state (31.875 dB) when the

VDD voltage is applied.

RF INPUT AND OUTPUT

The power handling is defined by the ATTIN port. Refer to the RF

input power specifications in Table 1.

Table 8. Truth Table

Digital Control Input1

Attenuation State (dB)

D7

D6

D5

D4

D3

D2

D1

D0

Low

Low

Low

Low

Low

Low

Low

Low

0 (reference)

Low

Low

Low

Low

Low

Low

Low

High

0.125

Low

Low

Low

Low

Low

Low

High

Low

0.25

Low

Low

Low

Low

Low

High

Low

Low

0.5

Low

Low

Low

Low

High

Low

Low

Low

1.0

Low

Low

Low

High

Low

Low

Low

Low

2.0

Low

Low

High

Low

Low

Low

Low

Low

4.0

Low

High

Low

Low

Low

Low

Low

Low

8.0

High

Low

Low

Low

Low

Low

Low

Low

16.0

High

High

High

High

High

High

High

High

31.875

1 Any combination of the states within this table provides an attenuation equal to the sum of the bits selected.

Figure 52. Simplified Circuit Diagram