ACT4060

- 6 -

www.active-semi.com

Copyright © 2006 Active-Semi, Inc.

Rev8, 24-Jul-07

STABILITY COMPENSATION

STEP 3. If the output capacitor’s ESR is high

enough to cause a zero at lower than 4 times the

cross over frequency, an additional compensation

pacitor has sufficiently low ESR, a small value

PCB layout parasitic effects.

Table 2 shows some calculated results based on

the compensation method above.

Table 2:

Typical Compensation for Different Output

Voltages and Output Capacitors



2.5V

22

μF Ceramic

8.2k

Ω

2.2nF

None

3.3V

22

μF Ceramic

12k

Ω

1.5nF

None

5V

22

μF Ceramic

15k

Ω

1.5nF

None

2.5V

47

μF SP CAP

15k

Ω

1.5nF

None

3.3V

47

μF SP CAP

15k

Ω

1.8nF

None

5V

47

μF SP CAP

15k

Ω

2.7nF

None

2.5V

470

μF/6.3V/30mΩ

15k

Ω

15nF

1nF

3.3V

470

μF/6.3V/30mΩ

15k

Ω

22nF

1nF

5V

470

μF/6.3V/30mΩ

15k

Ω

27nF

None

: C

Figure 3 shows an example ACT4060 application circuit generat-

ing a 2.5V/2A output.

COMP

ESRCOUT

OUT

2

COMP

R

R

C

C



(13)

Figure 2:

Stability Compensation

(10)

(F)

COMP

5

COMP

R

10

8

.

1

C







(11)

(F)

OUT

OUT

5

COMP

C

V

10

2

.

1

C







: C

The feedback loop of the IC is stabilized by the

components at the COMP pin, as shown in Figure 2.

The DC loop gain of the system is determined by

the following equation:

The following steps should be used to compensate

the IC:

STEP 1. Set the cross over frequency at 1/10 of the

The second pole P2 is the output pole:

COMP2

COMP

3

P

C

R

π

2

1

f



(8)

(Ω)

(9)

V

3

.

1

G

G

10

f

C

V

π

2

R

COMP

EA

SW

OUT

OUT

COMP





OUT

OUT

8

C

V

10

7

.

1





(4)

COMP

VEA

OUT

VDC

G

A

I

V

3

.

1

A



(5)

COMP

VEA

EA

1

P

C

A

π

2

G

f



(6)

OUT

OUT

OUT

2

P

C

V

π

2

I

f



(12)

(Ω)





















OUT

OUT

6

ESRCOUT

V

012

.

0

,

C

10

1

.

1

Min

R

(7)

COMP2

COMP

1

Z

C

R

π

2

1

f

