ST7FLCD1_05 datasheet(55/95 Pages) STMICROELECTRONICS

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ST7FLCD1

I²C Single-Master Bus Interface

Error Case:

AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by hardware with

an interrupt if the ITE bit is set. To resume, set the START or STOP bit.

Note:

The SCL line is not held low if AF = 1.

EV1:

EVF = 1, SB = 1, cleared by reading the SR register followed by writing to the DR register.

EV2:

EVF = 1, cleared by reading the SR register followed by writing to the CR register (for

example PE = 1).

EV2-1: EVF = 1, AF = 1, cleared by reading the SR register followed by writing STOP = 1 in the CR

EV3:

EVF = 1, BTF = 1, cleared by reading the SR register followed by reading the DR register.

EV3-1: Same as EV3, but ACK bit in CR register must be cleared before reading the DR register in

order to send a NAK pulse after the “Data N” byte.

EV3-2: Same as EV3, but STOP = 1 must be written in the CR register.

EV4:

EVF = 1, BTF = 1, cleared by reading the SR register followed by writing to the DR register.

Figure 30: Transfer Sequencing

Figure 31: Event Flags and Interrupt Generation

Master Receiver:

Master Transmitter:

Slave Not Responding:

Address

Data1

Data2

.....

Data N-1

Data N

EV1

EV2

EV3

EV3-1

EV3-2

Address

Data1

Data2

.....

DataN

EV1

EV2

EV4

Address

EV1

EV2-1

Legend:

S = Start, P = Stop, A = Acknowledge,

NA = Non-acknowledge

EVx = Event (with interrupt if ITE = 1)

BTF

EVF

Interrupt

ITE

* EVF can also be set by EV6 or an error from the SR2 register.

ST7FLCD1 Datasheet(PDF) 55 Page - STMicroelectronics

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