CSG14K_CSG8K datasheet(49/114 Pages) AMSOSRAM

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CSG14K_CSG8K

Functional Description

Datasheet

• PUBLIC

DS000571

• v2-01 • 2023-Feb-10

113

│ 48

Figure 50:

State Diagram: Streaming Mode

Because of the nature of the streaming mode, there is no such thing as invalid or special

control timing. Once started, it will be forever looping and all further REQ_EXP and

REQ_FRAME pulses are ignored.

7.2.8

Software Commands

Figure 51:

Software Command Registers

Reg.Name

Bank

Addr

Bits

CMD_REGS.CMD_RST_SOFT_N

[0]

CMD_REGS.CMD_REQ_EXP

[1]

CMD_REGS.CMD_REQ_FRAME

[2]

CMD_REGS.CMD_HALT_BLOCK

[3]

CMD_REGS.CMD_HALT_NBLOCK

[4]

The register bits CMD_REQ_EXP and CMD_REQ_FRAME are equivalent to their sensor

input counterparts REQ_EXP and REQ_FRAME. The sensor REQ_EXP and REQ_FRAME

inputs can therefore be tied low to use the register uploads for frame timing control. By setting

the CMD register bit, the respective command is sent to the internal control logic. The CMD

bits are not automatically cleared after a request is progressed, this should be done by the

user. Note that the sensor’s internal registers are updated at the end of the SPI data transfer,

as detailed in section 7.2.4.

1st

EXPOSURE

GLOB

IDLE

RESET

READOUT

(N)

EXPOSURE

(N+1)

rising (REQ_EXP)

after (exposure time)

after (frame time)

after (ExpDelay) **

=> ExpDelay = frame time

– exp time

HALT command

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