STA015 datasheet(40/55 Pages) STMICROELECTRONICS

No. de pieza	STA015

Descripción Electrónicos	MPEG 2.5 LAYER III AUDIO DECODER WITH ADPCM CAPABILITY

PDF	55 Pages

Scroll/Zoom	100%

Fabricante Electrónico	STMICROELECTRONICS [STMicroelectronics]

Página de inicio	http://www.st.com

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STA015 STA015B STA015T

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Hardware Reset: 0x00

X = don’t care;

0 = no ancillary data

1 = Ancillary Data Available

The ISR is used by the microcontroller to understand when a new ancillary data block is available.

After all ancillary data has been retrieved this bit must be cleared.

ADPCM_CONFIG

Address: 0xB8 (184)

Type: R/W

Software Reset: 0x00

Hardware Reset: 0x00

This register controls ADPCM engine and how data must be compressed.

AFM_EN

ADPCM Frame Mode Enable

0 = no frames (raw format)

1 = select the framed output format for ADPCM encoded data

ASM_EN:

ADPCM Stereo Mode Enable

0 = Disable stereo mode

1 = Enable stereo mode

AA0,AA1:

ADPCM Algorithm selection The ADPCM encoding/decoding algorithm can be selected

according to the following table:

The above bitrates refers to an 8 KHz 16 bits mono input stream.

Please note that 32KHz stereo mode is only available (both in encoding and decoding) with DVI algorithm

MSB

LSB

XXXXX

MSB

LSB

AA1

AA0

ASM_EN

AFM_EN

AA1

AA0

DVI algorithm

G723-24 algorithm (24kbp/s)

G721 algorithm (32kbp/s)

G723-40 algorithm (40kbp/s)

STA015 Datasheet(PDF) 40 Page - STMicroelectronics

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