STA015B datasheet(22/55 Pages) STMICROELECTRONICS

No. de pieza	STA015B

Descripción Electrónicos	MPEG 2.5 LAYER III AUDIO DECODER WITH ADPCM CAPABILITY

PDF	55 Pages

Scroll/Zoom	100%

Fabricante Electrónico	STMICROELECTRONICS [STMicroelectronics]

Página de inicio	http://www.st.com

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STA015 STA015B STA015T

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CMD_INTERRUPT

Address: 0x16 (22)

Type: R/W

Software Reset: 0x00

Hardware Reset: 0x00

X = don’t care;

0 = normal operation;

1 = write into I2C/Ancillary Data

The INTERRUPT is used to give STA015 the command to write into the I2C/Ancillary Data Buffer (Regis-

ters: 0x7E ... 0xB5). Every time the Master has to extract the new buffer content it writes into this register,

setting it to a non-zero value.

DATA_REQ_ENABLE

Address: 0x18 (24)

Type: R/W

Software Reset: 0x00

Hardware Reset: 0x00

The DATA_REQ_ENABLE register is used to configure Pin n. 28 working as buffered output clock or data

request signal, used for multimedia mode.

The buffered Output Clock has the same frequency than the input clock (XTI)

SYNCSTATUS

Address: 0x40 (64)

Type: RO

Software Reset: 0x00

Hardware Reset: 0x00

MSB

LSB

XXXXX

MSB

LSB

Description

buffered output clock

request signal

MSB

LSB

Description

XXX

SS1

SS0

Research of sync word

Wait for Confirmation

Synchronised

STA015B Datasheet(PDF) 22 Page - STMicroelectronics

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