AT80C5112_08 datasheet(9/97 Pages) ATMEL

9 / 97 page

AT8xC5112

4191C–8051–02/08

Functional Block Diagram

Operating Modes

Functional Modes

Normal Modes

•

CPU and Peripheral clocks depend on the software selection using CKCON0,

CKCON1, CKSEL and CKRL registers.

•

CKS bit selects either Xtal_Osc or RC_Osc.

•

CKRL register determines the frequency of the selected clock, unless X2 bit is set.

In this case the prescaler/divider is not used, so CPU core needs only 6 clock

periods per machine cycle. According to the value of the peripheral X2 individual bit,

each peripheral needs 6 or 12 clock periods per instruction.

•

It is always possible to switch dynamically by software from Xtal_Osc to RC_Osc,

and vice versa by changing CKS bit, a synchronization cell allowing to avoid any

spike during transition.

Idle Modes

•

IDLE modes are achieved by using any instruction that writes into PCON.0 sfr

•

IDLE modes A and B depend on previous software sequence, prior to writing into

PCON.0 register:

–

IDLE MODE A: Xtal_Osc is running (OSCAEN = 1) and selected (CKS = 1)

–

IDLE MODE B: RC_Osc is running (OSCBEN = 1) and selected (CKS = 0)

•

The unused oscillator Xtal_Osc or RC_Osc can be stopped by software by clearing

OSCAEN or OSCBEN, respectively.

•

Exit from IDLE mode is achieved by Reset, or by activation of an enabled interrupt.

•

In both cases, PCON.0 is cleared by hardware.

Xtal2

Xtal1

PwdRC

WD Clock

PwdOsc

Ckrl

Reload

8-bit

Prescaler-Divider

ResetB

OscOut

Xtal_Osc

RC_Osc

OSCBEN

OSCAEN

CKS

Mux

Filter

OSCA

OSCB

CkIdle

Idle

CPU Clock

Peripherals Clock

Pwd

CkOut

CkAdc

Quiet

: 128

A/D Clock

Sub Clock

Timer 0 Clock

AT80C5112 Datasheet(PDF) 9 Page - ATMEL Corporation

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