PSD813F1 datasheet(91/120 Pages) STMICROELECTRONICS

91 / 120 page

Preliminary

PSD813F1-A

-90

-12

-15

Symbol

Parameter

Conditions

Min

Max

Min

Max

Min

Max

Unit

tLVLX

ALE or AS Pulse Width

tAVLX

Address Setup Time

(Note 1)

tLXAX

Address Hold Time

(Note 1)

tAVWL

Address Valid to Leading

Edge of WR

(Notes 1 and 3)

t SLWL

CS Valid to Leading Edge of WR

(Note 3)

t DVWH

WR Data Setup Time

(Note 3)

t WHDX

WR Data Hold Time

(Note 3)

t WLWH

WR Pulse Width

(Note 3)

tWHAX

Trailing Edge of WR to Address

Invalid

(Note 3)

tWHAX

Trailing Edge of WR to DPLD

Address Input Invalid

(Notes 3 and 6)

tWHPV

Trailing Edge of WR to Port Output

Valid Using I/O Port Data Register

(Note 3)

tWLMV

WR Valid to Port Output Valid Using

Micro

⇔Cell Register Preset/Clear

(Notes 3 and 4)

Data Valid to Port Output Valid

tDVMV

Using Micro

⇔Cell Register

(Notes 3 and 5)

Preset/Clear

tAVPV

Address Input Valid to Address

(Note 2)

Output Delay

Write, Erase and Program Timing (5 V ± 10% Versions)

NOTES: 1.

Any input used to select an internal PSD813F function.

In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.

WR timing has the same timing as E, LDS, UDS, WRL, and WRH signals.

Assuming data is stable before active write signal.

Assuming write is active before data becomes valid.

Address Hold Time for DPLD inputs that are used to generate chip selects for internal PSD memory.

Microcontroller Interface – PSD813F1 AC/DC Parameters

(5V ± 10% Versions)

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