ST24LC21B datasheet(14/22 Pages) STMICROELECTRONICS

14 / 22 page

the SDA signal must be stable during the clock low

to high transition and the data must change ONLY

when the SCL line is low.

Memory Addressing. To start communication be-

tween the bus master and the slave ST24xy21, the

master must initiate a START condition. Following

this, the master sends onto the SDA bus line 8 bits

(MSB first) corresponding to the Device Select

code (7 bits) and a READ or WRITE bit. The 4 most

significant bits of the Device Select code are the

device type identifier, corresponding to the I2C bus

definition. For these memories the 4 bits are fixed

as 1010b. The 8th bit sent is the read or write bit

(RW), this bit is set to ’1’ for read and ’0’ for write

operations. If a match is found, the corresponding

memory will acknowledge the identification on the

SDA bus during the 9th bit time.

Write Operations

Following a START condition the master sends a

Device Select code with the RW bit set to ’0’. The

memory acknowledges this and waits for a byte

address. After receipt of the byte address the de-

vice again responds with an acknowledge.

In I2C bidirectional mode, any write command with

VCLK=0 (for the ST24LC21B and ST24FC21,

ST24FC21B) or with WC=0 (for the ST24LW21 and

ST24FW21) will not modify data and will be ac-

knowledged on data bytes, as shown in Figure 12.

Byte Write. In the Byte Write mode the master

sends one data byte, which is acknowledged by the

WRITE Cycle

in Progress

AI01099B

Operation is

Addressing the

Memory

START Condition

DEVICE SELECT

with RW = 0

ACK

Returned

YES

ReSTART

STOP

Proceed

WRITE Operation

Proceed

Random Address

READ Operation

Send

Byte Address

First byte of instruction

with RW = 0 already

decoded by ST24xxx

Figure 10. Write Cycle Polling using ACK

14/22

ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21

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