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ST72C171 Datasheet(PDF) 17 Page - STMicroelectronics

No. de pieza ST72C171
Descripción Electrónicos  8-BIT MCU with 8K FLASH, ADC, WDG, SPI, SCI, TIMERS SPGAs Software Programmable Gain Amplifiers, OP-AMP
PDF  152 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
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ST72C171 Datasheet(HTML) 17 Page - STMicroelectronics

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4.2.1 Reset Sequence Manager (RSM)
The RSM block of the CROSS Module includes
three RESET sources as shown in Figure 10:
s
EXTERNAL RESET SOURCE pulse
s
Internal LVD RESET (Low Voltage Detection)
s
Internal WATCHDOG RESET
These sources act on the RESET PIN and it is al-
ways kept low during the READ OPTION RESET
phase.
The RESET service routine vector is fixed at the
FFFEh-FFFFh addresses in the ST7 memory
map.
Figure 10. Reset Block Diagram
The basic RESET sequence consists of 4 phases
as shown in Figure 11:
s
OPTION BYTE reading to configure the device
s
Delay depending on the RESET source
s
4096 cpu clock cycle delay
s
RESET vector fetch
The duration of the OPTION BYTE reading phase
(tROB) is defined in the Electrical Characteristics
section. This first phase is initiated by an external
RESET pin pulse detection, a Watchdog RESET
detection, or when VDD rises up to VLVDopt.
The 4096 cpu clock cycle delay allows the oscilla-
tor to stabilise and to ensure that recovery has tak-
en place from the Reset state.
The RESET vector fetch phase duration is 2 clock
cycles.
Figure 11. RESET Sequence Phases
fCPU
RESET
RON
VDD
WATCHDOG RESET
LVD RESET
INTERNAL
RESET
READ OPTION RESET
RESET
READ
OPTION BYTE
INTERNAL RESET
4096 CLOCK CYCLES
FETCH
VECTOR
DELAY
tROB



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