ST72C171 datasheet(40/152 Pages) STMICROELECTRONICS

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ST72C171

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OP-AMP MODULE (Cont’d)

7.3.4 Autozero Mode

When the following description refers to both OA1

or OA2, x stands for 1 or 2.

In order to eliminate the ADC errors due to the

SPGA offset voltage, this voltage may be deter-

mined, prior to the A/D conversion (at power on or

periodically) and stored in RAM. The stored value

may be used afterwards to eliminate the errors of

any A/D conversion that uses the SPGA (ADC

zooming). The measurement may be done inde-

pendently for OA1 and OA2.

The measurement algorithm has 3 steps:

1. The SPGA is in repeater mode (NSx[1:0] = 01),

with the lowest gain (Gx[2:0]=000), the autoze-

roing switch is left open (AZx = 0). The positive

input of the op-amp is connected to a DC value,

using the VRx reference voltage generator

(PSx[1:0] = 00), and the output is sent to the

ADC. Under these conditions, the ADC meas-

ures the value:

Vo = VRx -Voff

of the SPGA output.

2. Set the gain (G) according the application

requirement. The AZx bit is set to 1. The output

voltage of the SPGA becomes:

V’o = VRx - Voff - G * Voff

3.Voff calculated with 1) - 2)

Voff =( Vo- V’o) /G

As the offset voltage of the SPGAs may vary with

the common mode voltage value, the measure-

ment must be done choosing VRx to match the ap-

plication conditions. Alternatively, nine measure-

ments may be done with the noninverting input

voltage varying between 0 and VDDA in 1/8 VDD

steps, in order to fully characterise the offset volt-

age of the op-amp.

7.3.5 Comparator mode with Interrupts

The 2 SPGAs can be configured in comparator

mode (GX[2:0]=111). In this case the positive in-

put can be connected to the internal reference

voltage. The negative input can be used to receive

the analog voltage to be compared with the volt-

age connected to the positive input.

By means of a Schmitt trigger, the SPGA output is

readable as a logical level in the OAxVR bit in the

OAIRR register. These bits are read only.

An interrupt request remains pending as long as

the output value (OAxVR) is equal to the corre-

sponding polarity bit (OAxPR) and when the inter-

rupt enable bit (OAxIE) is set. There is one inter-

rupt vector for each SPGA.

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