STA680 datasheet(34/43 Pages) STMICROELECTRONICS

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Digital I/O and memory interfaces

STA680

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5.4.5

Host micro I2C interface (I2C1)

The Host Micro I2C Interface enables the host processor to pass commands, diagnostic

information, and data between the host processor and HD Radio Decoder.

The I2C1 interface is a standard I2C interface where the STA680 acts as a slave to the Host

Micro and only responds to requests for information. It is also configurable by the Host Micro

to work as a master to better support bi-directional flow of data and audio.

The I2C1 interface supports 7-bit addressing and 8-bit data. It can run in both standard

mode (serial clock frequency up to 100 kHz) and fast mode (up to 400 kHz). The I2C device

addresses are reported in Table 16.

Although not part of the IIC standard, an additional control line called IIC1_DA is provided.

This line is useful for indicating when data is available and can be polled by either master or

slave.

5.4.6

Auxiliary I2C interface (I2C2)

The Auxiliary I2C interface can be programmed to be a master or slave. The usage of this

interface by the host processor is optional and by default it is disabled after reset.

The I2C2 interface supports 7-bit addressing and 8-bit data. It can run in both standard

mode (serial clock frequency up to 100 kHz) and fast mode (up to 400 kHz). The I2C device

addresses are reported in Table 17.

Although not part of the IIC standard, an additional control line called IIC1_DA is provided.

This line is useful for indicating when data is available and can be polled by either master or

slave.

Table 16.

I2C1 interface device address

I2C1

Primary address

Secondary address

Read Address

0101111b

0101101b

Write Address

0101110b

0101100b

Table 17.

I2C2 interface device address

I2C2

Primary Address

Secondary Address

Read Address

0101011b

0101001b

Write Address

0101010b

0101000b

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