STA680 datasheet(35/43 Pages) STMICROELECTRONICS

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STA680

Digital I/O and memory interfaces

35/43

5.5

SDRAM interface

The SDRAM interface supports up to 32M x 16 SDRAM and supports both standard and

mobile protocols. For pin description see Table 18

The minimum required SDRAM size for single channel application is 64 Mbit while for a dual

channel application at least 128 Mbit are needed.

Figure 13 shows timing diagrams and waveform for the SDRAM interface.

Figure 13.

Timing diagrams and waveform for the SDRAM interface

In Table 19 are reported the timing values for the SDRAM interface.

Table 18.

SDRAM Interface pin description

Pin Name

Designation

Type

Drive

SDR_D[0:15]

SDRAM interface data bus

I/O

4 mA

SDR_A[0:12]

SDRAM interface address bus

4 mA

SDR_BA[0:1]

Bank address

4 mA

SDR_CAS_N

Active-low column address strobe

8 mA

SDR_RAS_N

Active-low row address strobe

8 mA

SDR_WE_N

Active-low write enable

8 mA

SDR_CS_N

Active-low chip select

8 mA

SDR_DQM0

low-byte data input/output mask

4 mA

SDR_DQM1

high-byte data input/output mask

4 mA

SDR_CKE

Clock enable

4 mA

SDR_CLK_RAM3V3

Clock to SDRAM for 3.3 V interface

8 mA

SDR_FEED_CLK

Feedback clock from SDRAM

8 mA

SDR_CLK_RAM

SDR_CAS

SDR_A

SDR_D

SDR_BA

SDR_WE_N

SDR_CLK_CS

SDR_RAS

ROW

BANK

COL

BANK

Din

Tds

Tdh

Toh

Tac

Dout

Tcl

Tch

Tck

BANK

ROW

COL

CAS latency = 3

write

read

AC00720

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