M32CSLASH8B datasheet(78/406 Pages) RENESAS

78 / 406 page

Under development

M32C/8B Group

8. Bus

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 61 of 385

8.3

Page Mode Control Function

The page mode control function allows high-speed read access to the external memory compatible with the page

mode control. While the MCU accesses data within the eight-byte block of consecutive addresses which have the

same 21 high-order bits, less cycles are taken for the subsequent bus read accesses to a maximum of seven-byte

addresses than the first bus access.

The EWCRi register (i = 0 to 3) determines how many wait states are inserted for the first bus access. Registers

PWCR0 and PWCR1 determine how many wait states are inserted for the subsequent bus accesses. Use the

following procedure to enable the page mode control.

(1) Set bits EWCRi4 to EWCRi0 in the EWCRi register.

(2) Set bits PWCRj02 to PWCRj00 and bits PWCRj06 to PWCRj04 in the PWCRj register (j = 0, 1).

(3) Set bits PWCRj03 and PWCRj07 to 1 (page mode control enabled).

When using the page mode control function, access all the external spaces using page mode control. It is not

allowed to combine the page mode controlled access and the normal access to external spaces.

Set bits PM05 and PM04 to 00b (multiplexed bus is not used). The page mode control function and multiplexed bus

cannot be used at the same time.

Figure 8.12 and 8.13 show registers PWCR0 and PWCR1. Figure 8.14 shows a diagram of external bus timing with

page mode function.

The page mode control function is available only in the ROMless version.

NOTE

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