M32CSLASH8B datasheet(88/406 Pages) RENESAS

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Under development

M32C/8B Group

9. Clock Generation Circuits

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 71 of 385

Figure 9.6

PLC0 Register

b6 b5 b4

PLL Control Register 0 (1)(2)

Symbol

PLC0

Address

0026h

Bit Symbol

Bit Name

PLC00

After Reset

0001 X010b

NOTES:

1. Set the PLC0 register after the PRC0 bit in the PRCR register is set to 1 (write enable).

2. If the PM21 bit in the PM2 register is set to 1 (disables a clock change), a write to the PLC0 register has no effect.

3. Set bits PLC02 to PLC00 while the PLC07 bit is 0. Bits PLC02 to PLC00 can be written only once.

4. Enter wait mode or stop mode after the CM17 bit is set to 0 (main clock as CPU clock source) and then the PLC07 bit to 0.

5. The frequency of PLL clock is calculated by the following equation.

Function

PLL clock multiplication factor

select bits(3)(5)

PLC01

PLC02

b2 b1 b0

0 1 0: Multiply-by-4

1 0 0: Multiply-by-8

Do not set to values other than the above

−

(b3)

PLC05

Set to 0

−

(b6)

PLC07

Reference clock division rate

select bits(3)(5)

Reserved bit

b5 b4

0 0: No division

0 1: Divide-by-2

1 0: Divide-by-4

Do not set to values other than the above

0: PLL stops

1: PLL runs

Operation enable bit(4)

−

Unimplemented.

Write 0. Read as undefined value.

PLC04

PLL clock frequency = Main clock frequency

× PLL clock multiplication factor

Reference clock division rate

Set by bits PLC02 to PLC00.

Set by bits PLC05 and PLC04.

e.g.) Main clock frequency: 10 MHz

Bits PLC02 to PLC00: 100b (multiply-by-8)

PLL clock frequency = 10 MHz

= 20 MHz

Bits PLC05 and PLC04: 10b (divide-by-4)

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