M32CSLASH86 datasheet(63/505 Pages) RENESAS

63 / 505 page

Page 40

5. Reset

)

(

Figure 5.3 Brown-out Detection Reset (Hardware Reset 2)

5.3 Software Reset

Pins, the CPU and SFR are reset when the PM03 bit in the PM0 register is set to "1" (microcomputer reset).

Then the microcomputer executes the program in an address determined by the reset vector.

Set the PM03 bit to "1" while the main clock is selected as the CPU clock and the main clock oscillation is

stable.

In the software reset, the microcomputer does not reset a part of the SFR. Refer to 4. SFR for details.

Processor mode remains unchanged since the PM01 and PM00 bits in the PM0 register are not reset.

5.4 Watchdog Timer Reset

Pins, the CPU and SFR are reset when the CM06 bit in the CM0 register is set to "1" (reset) and the

watchdog timer underflows. Then the microcomputer executes the program in an address determined by

the reset vector.

In the watchdog timer reset, the microcomputer does not reset a part of the SFR. Refer to 4. SFR for details.

Processor mode remains unchanged since the PM01 and PM00 bits in the PM0 register are not reset.

Vdet4

Vdet3

5.0V

VCC

Internal Reset Signal

VC13 Bit

VC26 Bit

VC27 Bit

Set to "1" by program (reset level detection circuit enabled)

Set to "1" by program

(low voltage detection circuit enabled)

When Stop Mode is not Used

VSS

Indeterminate

RESET

Vdet3s

Vdet3r

Indeterminate

M32C/86 Datasheet(PDF) 63 Page - Renesas Technology Corp