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M32C/86 Datasheet(PDF) 93 Page - Renesas Technology Corp

No. de pieza M32C/86
Descripción Electrónicos  RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES
PDF  505 Pages
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Fabricante Electrónico  RENESAS [Renesas Technology Corp]
Página de inicio  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M32C/86 Datasheet(HTML) 93 Page - Renesas Technology Corp

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_________
8.2.7 HOLD Signal
__________
The HOLD signal transfers bus privileges from the CPU to external circuits. When a low-level ("L") signal is
__________
applied to the HOLD pin, the microcomputer enters a hold state after bus access is completed. While the
__________
_________
HOLD pin is held "L", the microcomputer is in a hold state and the HLDA pin outputs an "L" signal.
Table 8.7 shows the microcomputer status in a hold state.
__________
Bus is used in the following priority order: HOLD, DMAC, CPU.
Figure 8.12 Bus Priority Order
Table 8.7 Microcomputer Status in Hold State
8.2.8 External Bus Status when Accessing Internal Space
Table 8.8 shows external bus states when an internal space is accessed.
Table 8.8 External Bus States when Accessing Internal Space
8.2.9 BCLK Output
The CPU clock operates the CPU. P53 outputs the CPU clock signal as BCLK when the PM07 bit in the
PM0 register is set to "0" (BCLK) and the CM01 and CM00 bits in the CM0 register are set to "002" (I/O
port P53).
No BCLK is output in single-chip mode. Refer to 9. Clock Generation Circuit for details.



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