H8SLASH3021 datasheet(302/712 Pages) RENESAS

No. de pieza	H8/3021

Descripción Electrónicos	16-Bit Single-Chip Microcomputer

PDF	712 Pages

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Fabricante Electrónico	RENESAS [Renesas Technology Corp]

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8. 16-Bit Integrated Timer Unit (ITU)

Rev.2.00 Mar. 22, 2007 Page 278 of 684

REJ09B0352-0200

Contention between General Register Write and Input Capture: If an input capture signal

occurs in the T

3 state of a general register write cycle, input capture takes priority and the write to

the general register is not performed. See figure 8.68.

Address

Internal write signal

Input capture signal

TCNT

GR address

General register write cycle

Figure 8.68 Contention between General Register Write and Input Capture

Note on Waveform Period Setting: When a counter is cleared by compare match, the counter is

cleared in the last state at which the TCNT value matches the general register value, at the time

when this value would normally be updated to the next count. The actual counter frequency is

therefore given by the following formula:

f =

(N + 1)

(f: counter frequency.

φ: system clock frequency. N: value set in general register.)

H8/3021 Datasheet(PDF) 302 Page - Renesas Technology Corp