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MPC8313ECVRAFD Datasheet(PDF) 17 Page - Freescale Semiconductor, Inc

No. de pieza MPC8313ECVRAFD
Descripción Electrónicos  PowerQUICC??II Pro Processor Hardware Specifications
PDF  100 Pages
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Fabricante Electrónico  FREESCALE [Freescale Semiconductor, Inc]
Página de inicio  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8313ECVRAFD Datasheet(HTML) 17 Page - Freescale Semiconductor, Inc

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MPC8313E PowerQUICCII Pro Processor Hardware Specifications, Rev. 2.1
Freescale Semiconductor
17
DDR and DDR2 SDRAM
Figure 4 illustrates the DDR input timing diagram showing the tDISKEW timing parameter.
Figure 4. DDR Input Timing Diagram
6.2.2
DDR and DDR2 SDRAM Output AC Timing Specifications
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications for Rev. 1.0 Silicon
Parameter
Symbol 1
Min
Max
Unit
Notes
MCK[
n] cycle time, MCK[n]/MCK[n] crossing
tMCK
610
ns
2
ADDR/CMD output setup with respect to MCK
tDDKHAS
ns
3
333 MHz
2.1
266 MHz
2.5
ADDR/CMD output hold with respect to MCK
tDDKHAX
ns
3
333 MHz
2.4
266 MHz
3.15
MCS[
n] output setup with respect to MCK
tDDKHCS
ns
3
333 MHz
2.4
266 MHz
3.15
MCS[
n] output hold with respect to MCK
tDDKHCX
ns
3
333 MHz
2.4
266 MHz
3.15
MCK to MDQS Skew
tDDKHMH
–0.6
0.6
ns
4
MDQ//MDM output setup with respect to
MDQS
tDDKHDS,
tDDKLDS
ps
5
333 MHz
800
266 MHz
900
MDQ//MDM output hold with respect to MDQS
tDDKHDX,
tDDKLDX
ps
5
333 MHz
900
266 MHz
1100
MDQS preamble start
tDDKHMP
–0.5
× tMCK – 0.6
–0.5
× tMCK + 0.6
ns
6
MCK[
n]
MCK[
n]
tMCK
MDQ[
x]
MDQS[
n]
D1
D0
tDISKEW
tDISKEW



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