AT25DF321 datasheet(12/37 Pages) ATMEL

12 / 37 page

3669A–DFLASH–07/07

AT25DF321

ter be polled rather than waiting the t

CHPE time to determine if the device has finished erasing. At

some point before the erase cycle completes, the WEL bit in the Status Register will be reset

back to the logical “0” state.

The device also incorporates an intelligent erasing algorithm that can detect when a byte loca-

tion fails to erase properly. If an erase error arises, it will be indicated by the EPE bit in the

Status Register.

Figure 8-4.

Chip Erase

Protection Commands and Features

9.1

Write Enable

The Write Enable command is used to set the Write Enable Latch (WEL) bit in the Status Regis-

ter to a logical “1” state. The WEL bit must be set before a program, erase, Protect Sector,

Unprotect Sector, or Write Status Register command can be executed. This makes the issuance

of these commands a two step process, thereby reducing the chances of a command being

accidentally or erroneously executed. If the WEL bit in the Status Register is not set prior to the

issuance of one of these commands, then the command will not be executed.

To issue the Write Enable command, the CS pin must first be asserted and the opcode of 06h

must be clocked into the device. No address bytes need to be clocked into the device, and any

data clocked in after the opcode will be ignored. When the CS pin is deasserted, the WEL bit in

the Status Register will be set to a logical “1”. The complete opcode must be clocked into the

device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte

boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of

the WEL bit will not change.

Figure 9-1.

Write Enable

SCK

MSB

CCCCCCCC

OPCODE

HIGH-IMPEDANCE

SCK

MSB

00000110

OPCODE

HIGH-IMPEDANCE

AT25DF321 Datasheet(PDF) 12 Page - ATMEL Corporation