AT89C51ED2-RDTUM datasheet(28/137 Pages) ATMEL

28 / 137 page

4235K–8051–05/08

AT89C51RD2/ED2

11. Power Monitor

The POR/PFD function monitors the internal power-supply of the CPU core memories and the

peripherals, and if needed, suspends their activity when the internal power supply falls below a

safety threshold. This is achieved by applying an internal reset to them.

By generating the Reset the Power Monitor insures a correct start up when AT89C51RD2/ED2

is powered up.

11.1

Description

In order to startup and maintain the microcontroller in correct operating mode, VCC has to be sta-

bilized in the VCC operating range and the oscillator has to be stabilized with a nominal amplitude

compatible with logic level VIH/VIL.

These parameters are controlled during the three phases: power-up, normal operation and

power going down. See Figure 11-1.

Figure 11-1. Power Monitor Block Diagram

Note:

1. Once XTAL1 High and low levels reach above and below VIH/VIL. a 1024 clock period delay

will extend the reset coming from the Power Fail Detect. If the power falls below the Power Fail

Detect threshold level, the Reset will be applied immediately.

The Voltage regulator generates a regulated internal supply for the CPU core the memories and

the peripherals. Spikes on the external Vcc are smoothed by the voltage regulator.

The Power fail detect monitor the supply generated by the voltage regulator and generate a

reset if this supply falls below a safety threshold as illustrated in the Figure 11-2 below.

VCC

Power On Reset

Power Fail Detect

Voltage Regulator

XTAL1

(1)

CPU core

Memories

Peripherals

Regulated

Supply

RST pin

Hardware

Watchdog

PCA

Watchdog

Internal Reset

AT89C51ED2-RDTUM Datasheet(PDF) 28 Page - ATMEL Corporation