SPT5420SIM datasheet(2/8 Pages) CADEKA

2 / 8 page

6/26/01

SPT5420

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C

Note: 1. Operation at any Absolute Maximum Rating is not implied. See

Electrical Specifications for proper nominal applied conditions

in typical applications.

ELECTRICAL SPECIFICATIONS

TA = TMIN to TMAX, VCC = +5.0 V, VDD = +11.5 V, VSS = –8.0 V, VREFT=3.5 V, VREFB = –1.5 V, RL = +10 kΩ, CL = 50 pF, unless otherwise specified.

TEST

SPT5420

PARAMETERS

CONDITIONS

LEVEL

MIN

TYP

MAX

UNITS

Accuracy

Resolution

Bits

Integral Linearity Error (ILE)

–2.0

±0.5

+2.0

LSB

Differential Linearity Error (DLE)

–1.0

±0.3

+1.0

LSB

Zero-Scale Error

–25

+25

Full Scale Error

–25

+25

Gain Error

–25

+25

Reference Inputs

Input Current

±100

VREFT1

+3.5

+5.0

VREFB2

–5.0

–1.5

RGND Inputs

DC Input Impedance

Ω

Input Range

–2.0

2.0

Output Characteristics

Output Swing3,4

+7/–3

Short Circuit Current

Resistive Load

Ω

DC Output Impedance

1.0

Ω

Digital Inputs

Logic 1 Voltage

2.4

Logic 0 Voltage

0.8

Maximum Input Current

–10

µA/pin

Input Capacitance

Supply Voltages

VCC ........................................................................ +6 V

VDD ...................................................................... +15 V

VSS ...................................................................... –15 V

Input Voltages

VREFT .................................... VSS –0.3 V to VDD +0.3 V

VREFB ................................... VDD +0.3 V to VSS –0.3 V

Digital inputs .................................... –0.3 V to VCC +0.3 V

Temperature

Operating Temperature .......................... –40 to +85 °C

Storage ................................................ –65 to +150 °C

Notes:

1. VREFT < 8 V + (VSS x 0.5); e.g., if VSS = –8 V, then VREFT < 4 V

2. VREFB > (VDD x 0.5) – 9.5 V; e.g., if VDD = 11 V, then VREFB > –4 V

3. VSS + 2.5 V ≤ VOUT ≤ VSS + 16.0 V for 18.5 V ≤ VDD – VSS ≤ 20.0 V

VSS + 2.5 V ≤ VOUT ≤ VDD – 2.5 V for VDD – VSS ≤ 18.5 V

4. VOUT = 2 X (VREFB +[VREFT – VREFB] X

INPUT CODE

8192

) – VRGND

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