DS3101 datasheet(4/150 Pages) MAXIM

4 / 150 page

DS3101

19-4596; Rev 4; 5/09

4 of 150

LIST OF FIGURES

Figure 2-1. DS3101 Block Diagram ............................................................................................................................. 7

Figure 3-1. Typical Application Example ..................................................................................................................... 8

Figure 7-1. T0 DPLL State Transition Diagram ......................................................................................................... 28

Figure 7-2. T4 DPLL State Transition Diagram ......................................................................................................... 31

Figure 7-3. Typical MTIE for T0 DPLL Output ........................................................................................................... 37

Figure 7-4. Typical TDEV for T0 DPLL Output .......................................................................................................... 38

Figure 7-5. DPLL Block Diagram ............................................................................................................................... 40

Figure 7-6. OC10 8kHz Options ................................................................................................................................ 48

Figure 7-7. GR-378 Composite Clock Pulse Mask.................................................................................................... 54

Figure 7-8. SPI Clock Polarity and Phase Options.................................................................................................... 56

Figure 7-9. SPI Bus Transactions.............................................................................................................................. 57

Figure 9-1. JTAG Block Diagram............................................................................................................................. 125

Figure 9-2. JTAG TAP Controller State Machine .................................................................................................... 127

Figure 10-1. Recommended Termination for LVDS Pins ........................................................................................ 131

Figure 10-2. Recommended Termination for LVPECL Pins.................................................................................... 132

Figure 10-3. Recommended External Components for AMI Composite Clock Pins ............................................... 133

Figure 10-4. Parallel Interface Timing Diagram (Nonmultiplexed) .......................................................................... 136

Figure 10-5. Parallel Interface Timing Diagram (Multiplexed) ................................................................................. 137

Figure 10-6. SPI Interface Timing Diagram ............................................................................................................. 138

Figure 10-7. JTAG Timing Diagram......................................................................................................................... 139

Figure 11-1. DS3101 Pin Assignment—Left Half .................................................................................................... 143

Figure 11-2. DS3101 Pin Assignment—Right Half.................................................................................................. 144

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