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STM32W108CB Datasheet(PDF) 79 Page - STMicroelectronics |
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STM32W108CB Datasheet(HTML) 79 Page - STMicroelectronics |
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79 / 179 page  STM32W108CB, STM32W108HB Serial interfaces Doc ID 16252 Rev 2 79/179 7.7.15 DMA first receive error register A (SCx_RXERRA) Address offset: 0xC834 (SC1_RXERRA) and 0xC034 (SC2_RXERRA) Reset value: 0x0000 0000 7.7.16 DMA first receive error register B (SCx_RXERRB) Address offset: 0xC838 (SC1_RXERRB) and 0xC038 (SC2_RXERRB) Reset value: 0x0000 0000 [12:0] SC_RXCNTSAVED: Receive DMA count saved in SPI slave mode when nSSEL deasserts. The count is only saved the first time nSSEL deasserts. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SC_RXERRA rw rw rw r r r r r rr rr rr r r [12:0] SC_RXERRA: The offset from the start of DMA receive buffer A of the first byte received with a parity, frame, or overflow error. Note that an overflow error occurs at the input to the receive FIFO, so this offset is 4 bytes before the overflow position. If there is no error, it reads zero. This register will not be updated by subsequent errors until the buffer unloads and is reloaded, or the receive DMA is reset. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SC_RXERRB rw rw rw r r r r r rr rr rr r r [12:0] SC_RXERRB: The offset from the start of DMA receive buffer B of the first byte received with a parity, frame, or overflow error. Note that an overflow error occurs at the input to the receive FIFO, so this offset is 4 bytes before the overflow position. If there is no error, it reads zero. This register will not be updated by subsequent errors until the buffer unloads and is reloaded, or the receive DMA is reset. |
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