MPC8533ECHXAAJB datasheet(44/116 Pages) FREESCALE

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MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3

Freescale Semiconductor

Local Bus

Figure 23 provides the AC test load for the local bus.

Figure 23. Local Bus AC Test Load

Local bus clock to output high impedance for LAD/LDP

tLBKHOZ2

—2.6

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus

timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for

clock one (1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to

the output (O) going invalid (X) or output hold time.

2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.

3. All signals are measured from BVDD/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL

bypass mode to 0.4

× BVDD of the signal in question for 1.8-V signaling levels.

4. Input timings are measured at the pin.

5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is

programmed with the LBCR[AHD] parameter.

7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between

complementary signals at BVDD/2.

Table 42. Local Bus General Timing Parameters (BVDD = 1.8 V DC) (continued)

Parameter

Symbol1

Min

Max

Unit

Notes

Output

Z0 = 50 Ω

BVDD/2

RL = 50 Ω

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