ATtiny5 datasheet(95/168 Pages) ATMEL

95 / 168 page

8127C–AVR–10/09

ATtiny4/5/9/10

trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running

mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set

13.12.4

ADCL

– ADC Data Register

When an ADC conversion is complete, the result is found in the ADC register.

• Bits 7:0 – ADC7:0: ADC Conversion Result

These bits represent the result from the conversion.

13.12.5

DIDR0

– Digital Input Disable Register 0

• Bits 7:4 – Res: Reserved Bit

These bits are reserved and will always read zero.

• Bits 3:0 – ADC3D..ADC0D: ADC3..0 Digital Input Disable

When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-

abled. The corresponding PIN register bit will always read as zero when this bit is set. When an

analog signal is applied to the ADC3..0 pin and the digital input from this pin is not needed, this

bit should be written logic one to reduce power consumption in the digital input buffer.

Table 13-4.

ADC Auto Trigger Source Selections

ADTS2

ADTS1

ADTS0

Trigger Source

Free Running mode

Analog Comparator

External Interrupt Flag 0

Timer/Counter 0 Compare Match A

Timer/Counter 0 Overflow

Timer/Counter 0 Compare Match B

Pin Change Interrupt 0 Request

Timer/Counter 0 Capture Event

Bit

765

4321

0x19

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

ADCL

Read/Write

RRRR

Initial Value

000

0000

Bit

765

432

0x17

–

ADC3D

ADC2D

ADC1D

ADC0D

DIDR0

Read/Write

R/W

Initial Value

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