Production Data

WM9704M

WOLFSON MICROELECTRONICS LTD

PD Rev 3.2 January 2001

19

In this way data streams of differing sample rates can be transmitted across AC-link at its fixed

48kHz audio frame rate. Figure 9 illustrates the time slot based AC-link protocol.

SYNC

BIT_CLK

SDATA_OUT

VALID

FRAME

SLOT (1)

SLOT (2)

WM9704M SAMPLES

SYNC ASSERTION HERE

WM9704M SAMPLES

FIRST SDATA_OUT

BIT OF FRAME HERE

END OF PREVIOUS AUDIO FRAME

Figure 10 Start of an Audio Output Frame

A new audio output frame begins with a low to high transition of SYNC as shown in Figure 10. SYNC

is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK,

the WM9704M samples the assertion of SYNC. This falling edge marks the time when both sides of

AC-link are aware of the start of a new audio frame. On the next rising edge of BIT_CLK, AC’97

transitions SDATA_OUT into the first bit position of slot 0 (“Valid Frame” bit). Each new bit position is

presented to AC-link on a rising edge of BIT_CLK, and subsequently sampled by the WM9704M on

the following falling edge of BIT_CLK. This sequence ensures that data transitions and subsequent

sample points for both incoming and outgoing data streams are time aligned.

Baseline AC’97 specified audio functionality MUST ALWAYS sample rate convert to and from a fixed

48ks/s on the AC’97 controller.

This requirement is necessary to ensure that interoperability between the AC’97 controller and the

WM9704M, among other things, can be guaranteed by definition for baseline specified AC’97

features.

SDATA_OUT’s composite stream is MSB justified (MSB first) with all non-valid slot bit positions

stuffed with 0s by the AC’97 controller.

In the event that there are less than 20 valid bits within an assigned and valid time slot, the AC’97

controller always stuffs all trailing non-valid bit positions of the 20-bit slot with 0s.

As an example, consider an 8-bit sample stream that is being played out to one of the WM9704M’s

DACs. The first 8 bit positions are presented to the DAC (MSB justified) followed by the next 12 bit

positions, which are stuffed with 0s by the AC’97 controller. This ensures that regardless of the

resolution of the implemented DAC (16, 18 or 20-bit), no DC biasing will be introduced by the least

significant bits.

When mono audio sample streams are output from the AC’97 controller, it is necessary that BOTH

left and right sample stream time slots be filled with the same data.

SLOT 1: COMMAND ADDRESS PORT

The command port is used to control features, and monitor status (see Figure 12) for the WM9704M

functions including, but not limited to, mixer settings, and power management (refer to the register

section). The control interface architecture supports up to 64, 16-bit read/write registers, addressable

on even byte boundaries. Only the even registers (00h, 02h, etc.) are valid, odd register (01h, 03h,

etc.) accesses are discouraged (if supported they should default to the preceding even byte

boundary - i.e. a read to 01h will return the 16-bit contents of 00h). The WM9704M’s control register

file is nonetheless readable as well as writeable to provide more robust testability.

Audio output frame slot 1 communicates control register address, and read/write command

information to the WM9704M.