Production Data

WM9704M

WOLFSON MICROELECTRONICS LTD

PD Rev 3.2 January 2001

23

SLOT 3: PCM RECORD LEFT CHANNEL

Audio input frame slot 3 is the left channel output of the WM9704M’s input Mux, post-ADC.

The WM9704M’s ADCs can be implemented to support 16, 18, or 20-bit resolution. The WM9704M

ships out its ADC output data (MSB first), and stuffs any trailing non-valid bit positions with 0s to fill

out its 20-bit time slot.

SLOT 4: PCM RECORD RIGHT CHANNEL

Audio input frame slot 4 is the right channel output of the WM9704M’s input Mux, post-ADC.

The WM9704M’s ADCs can be implemented to support 16, 18, or 20-bit resolution.

The WM9704M ships out its ADC output data (MSB first), and stuffs any trailing non-valid bit

positions with 0s to fill out its 20-bit time slot.

SLOT 5: OPTIONAL MODEM LINE 1 CODEC

Audio input frame slot 5 contains MSB justified, modem ADC output data. When the device is in

Modem Mode (11), then right channel ADC data is output into this slot as well as onto the normal

PCM right channel slot.

SLOT 10: OPTIONAL MODEM LINE 2 CODEC

Audio input frame slot 10 contains MSB justified, modem ADC output data. When the device is in

Modem Mode (11), then left channel ADC data is output into this slot as well as onto the normal PCM

left channel slot.

SLOT 6: OPTIONAL DEDICATED MICROPHONE RECORD DATA

Audio input frame slot 6 is an optional (post-ADC) third PCM system, input channel available for

dedicated use by a desktop microphone. This optional AC’97 feature is not supported by the

WM9704M. This may be determined by the AC’97 controller interrogating the WM9704M Vendor ID

register.

SLOTS 7 TO 11: RESERVED

Audio input frame slots 7 to 12 are reserved for future use and are always stuffed with 0s by AC ‘97.

Slot 10 is filled with left ADC data in modem mode.

SLOT 12:

GPIO functions supported

AC-LINK LOW POWER MODE

The AC-link signals can be placed in a low power mode. When the WM9704M’s Powerdown Register

(26h), is programmed to the appropriate value, both BIT_CLK and SDATA_IN will be brought to, and

held at a logic low voltage level.

BIT_CLK and SDATA_IN are transitioned low immediately following the decode of the write to the

Powerdown Register (26h) with PR4. When the AC’97 controller driver is at the point where it is

ready to program the AC-link into its low power mode, slots 1 and 2 are assumed to be the only valid

stream in the audio output frame. At this point in time it is assumed that all sources of audio input

have also been neutralised.

The AC’97 controller should also drive SYNC and SDATA_OUT low after programming the

WM9704M to this low power, “halted” mode.

Once the WM9704M has been instructed to halt BIT_CLK, a special “wake up” protocol must be

used to bring the AC-link to the active mode since normal audio output and input frames can not be

communicated in the absence of BIT_CLK.