Production Data

WM9704Q

WOLFSON MICROELECTRONICS LTD

PD Rev 2.3 January 2001

19

AC-LINK AUDIO OUTPUT FRAME (SDATA_OUT)

The audio output frame data streams correspond to the multiplexed bundles of all digital output data

targeting the WM9704Q’s DAC inputs, and control registers. As briefly mentioned earlier, each audio

output frame supports up to 12 20-bit outgoing data time slots. Slot 0 is a special reserved time slot

containing 16-bits, which are used for AC-link protocol infrastructure.

OUTPUT TAG SLOT (16-BITS)

Bit (15)

Frame Valid

Bit (14)

Slot 1 Valid Command Address bit

(Primary Codec only)

Bit (13)

Slot 2 Valid Command Data bit

(Primary Codec only)

Bit (12:3)

Slot 3-12 Valid bits as defined by AC’97

Bit 2

Reserved

(Set to 0)

Bit (1:0)

2-bit Codec ID field

(00 reserved for Primary; 01, 10, 11

indicate Secondary)

New definitions for Secondary Codec Register Access

Within slot 0 the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags the validity for the

entire audio frame. If the Valid Frame bit is a 1, this indicates that the current audio frame contains at

least one time slot of valid data. The next 12-bit positions sampled by the WM9704Q indicate which

of the corresponding 12 time slots contain valid data.

In this way data streams of differing sample rates can be transmitted across AC-link at its fixed

48kHz audio frame rate. Figure 9 illustrates the time slot based AC-link protocol.

SYNC

BIT_CLK

SDATA_OUT

VALID

FRAME

SLOT (1)

SLOT (2)

WM9704Q SAMPLES

SYNC ASSERTION HERE

WM9704Q SAMPLES

FIRST SDATA_OUT

BIT OF FRAME HERE

END OF PREVIOUS AUDIO FRAME

Figure 10 Start of an Audio Output Frame

A new audio output frame begins with a low to high transition of SYNC as shown in Figure 10. SYNC

is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK,

the WM9704Q samples the assertion of SYNC. This falling edge marks the time when both sides of

AC-link are aware of the start of a new audio frame. On the next rising edge of BIT_CLK, AC’97

transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit position is

presented to AC-link on a rising edge of BIT_CLK, and subsequently sampled by the WM9704Q on

the following falling edge of BIT_CLK. This sequence ensures that data transitions and subsequent

sample points for both incoming and outgoing data streams are time aligned.

Baseline AC’97 specified audio functionality MUST ALWAYS sample rate convert to and from a fixed

48ks/s on the AC’97 controller. This requirement is necessary to ensure that interoperability between

the AC’97 controller and the WM9704Q, among other things, can be guaranteed by definition for

baseline specified AC’97 features.

SDATA_OUT’s composite stream is MSB justified (MSB first) with all non-valid slot bit positions

stuffed with 0s by the AC’97 controller. In the event that there are less than 20 valid bits within an

assigned and valid time slot, the AC’97 controller always stuffs all trailing non-valid bit positions of

the 20-bit slot with 0s.