WM9704Q

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 2.3 January 2001

24

Once powered down, re-activation of the AC-link via re-assertion of the SYNC signal must not occur

for a minimum of 4 audio frame times following the frame in which the powerdown was triggered.

When AC-link powers up it indicates readiness via the Codec Ready bit (input slot 0, bit 15).

COLD WM9704Q RESET

A cold reset is achieved by asserting RESETB for the minimum specified time. By driving RESETB

low, BIT_CLK, and SDATA_OUT will be activated, or re-activated as the case may be, and all the

WM9704Q control registers will be initialised to their default power on reset values.

RESETB is an asynchronous WM9704Q input.

WARM WM9704Q RESET

A warm WM9704Q reset will re-activate the AC-link without altering the current WM9704Q register

values. A warm reset is signalled by driving SYNC high for a minimum of 1

µs in the absence of

BIT_CLK.

Within normal audio frames SYNC is a synchronous input. In the absence of BIT_CLK, SYNC is

treated as an asynchronous input used in the generation of a warm reset to the WM9704Q. The

WM9704Q will not respond with the activation of BIT_CLK until SYNC has been sampled low again

by the WM9704Q. This will preclude the false detection of a new audio frame.

SERIAL INTERFACE REGISTER MAP DESCRIPTION

(See Table 24)

The serial interface bits perform control functions described as follows. Note that the register map is

fully specified by the AC’97 specification, and this description is simply repeated below, with optional

unsupported features omitted.

RESET REGISTER (INDEX 00h)

Writing any value to this register performs a register reset, which causes all registers to revert to their

default values. Reading this register returns the ID code of the part, indication of modem support (not

supported by the WM9704Q) and a code for the type of 3D stereo enhancement.

BIT

FUNCTION

VALUE ON

WM9704Q

ID0

Dedicated Mic PCM in channel

0

ID1

Modem line Codec support

0

ID2

Bass and treble control

0

ID3

Simulated stereo (mono to stereo)

0

ID4

Headphone out support

0

ID5

Loudness (bass boost) support

0

ID6

18-bit DAC resolution

1

ID7

20-bit DAC resolution

0

ID8

18-bit ADC resolution

1

ID9

20-bit ADC resolution

0

SE4...SE0

3D stereo enhancement technique

11000

Table 10 Reset Register Function

Note that the WM9704Q defaults to indicate 18-bit compatibility. However, a control bit may be set in

the vendor-specific registers that changes bits ID6 and ID8 to be 0, indicating a 16-bit device. It is

unlikely that this function will be required, however, as the MSB justification of the ADC and DAC

data means that a nominally 18-bit device should be fully compatible with controllers that only

provide 16-bit support. Most PC type applications will only require 16-bit operation.

PLAY MASTER VOLUME REGISTERS (INDEX 02h, 04h AND 06h)

These registers manage the output signal volumes. Register 02h controls the stereo master volume

(both right and left channels), Register 04h controls the optional stereo headphone out, and Register

06h controls the mono volume output. Each step corresponds to 1.5dB. The MSB of the register is

the mute bit. When this bit is set to 1 the level for that channel is set at -

ML5 through ML0 is for left channel level, ML5 through ML0 is for the right channel and MM5 through

MM0 is for the mono out channel.