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MPC8308 Datasheet(PDF) 61 Page - Freescale Semiconductor, Inc |
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MPC8308 Datasheet(HTML) 61 Page - Freescale Semiconductor, Inc |
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61 / 88 page ![]() MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 0 Freescale Semiconductor 61 SPI 19.2 SPI AC Timing Specifications Table 52 and provide the SPI input and output AC timing specifications. Figure 49 provides the AC test load for the SPI. Figure 49. SPI AC Test Load Figure 50 through Figure 51 represent the AC timing from Table 52. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. Output high voltage VOH IOH = –8.0 mA 2.4 — V Output low voltage VOL IOL = 8.0 mA — 0.5 V Output low voltage VOL IOL = 3.2 mA — 0.4 V Table 52. SPI AC Timing Specifications 1 Characteristic Symbol 2 Min Max Unit SPI outputs valid—master mode (internal clock) delay tNIKHOV —6 ns SPI outputs hold—master mode (internal clock) delay tNIKHOX 0.5 — ns SPI outputs valid—slave mode (external clock) delay tNEKHOV 8.5 ns SPI outputs hold—slave mode (external clock) delay tNEKHOX 2— ns SPI inputs—master mode (internal clock) input setup time tNIIVKH 6— ns SPI inputs—master mode (internal clock) input hold time tNIIXKH 0— ns SPI inputs—slave mode (external clock) input setup time tNEIVKH 4— ns SPI inputs—slave mode (external clock) input hold time tNEIXKH 2— ns Notes: 1. Output specifications are measured from the 50% level of the rising edge of SPICLK to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOX symbolizes the internal timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X). Table 51. SPI DC Electrical Characteristics (continued) Characteristic Symbol Condition Min Max Unit Output Z0 = 50 Ω NVDD/2 RL = 50 Ω |
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