HCS12 datasheet(28/452 Pages) FREESCALE

No. de pieza	HCS12

Descripción Electrónicos	HCS12 Microcontrollers

PDF	452 Pages

Scroll/Zoom	100%

Fabricante Electrónico	FREESCALE [Freescale Semiconductor, Inc]

Página de inicio	http://www.freescale.com

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S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

Sixteen-bit values are stored in memory as two consecutive bytes; the high

byte occupies the lowest address, but need not be aligned to an even

boundary.

Thirty-two-bit values are stored in memory as four consecutive bytes; the

high byte occupies the lowest address, but need not be aligned to an even

boundary.

All input/output (I/O) and all on-chip peripherals are memory-mapped. No

special instruction syntax is required to access these addresses. On-chip

registers and memory typically are grouped in blocks which can be

relocated within the standard 64-Kbyte address space. Refer to device

documentation for specific information.

2.5 Instruction Queue

The CPU12 uses an instruction queue to buffer program information. The

mechanism is called a queue rather than a pipeline because a typical

pipelined CPU executes more than one instruction at the same time, while

the CPU12 always finishes executing an instruction before beginning to

execute another. Refer to Section 4. Instruction Queue for more

information.

HCS12 Datasheet(PDF) 28 Page - Freescale Semiconductor, Inc