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ST72101G1M1 Datasheet(PDF) 55 Page - STMicroelectronics |
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ST72101G1M1 Datasheet(HTML) 55 Page - STMicroelectronics |
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55 / 85 page ![]() Obsolete Product(s) - Obsolete Product(s) 55/85 ST72101/ST72212/ST72213 SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 36. Data Clock Timing Diagram CPOL = 1) CPOL = 0) MISO (from master) MOSI (from slave) SS (to slave) CAPTURE STROBE CPHA =1 CPOL = 1 CPOL = 0 MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit MISO (from master) MOSI SS (to slave) CAPTURE STROBE CPHA =0 Note: This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter. (from slave) VR02131B MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit SCLK (with SCLK (with 55 |
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