iC-MB3

BiSS INTERFACE MASTER, 1-Chan./3-Slaves

Rev D1, Page 7/26

Figure 3: Write cycle (Intel Mode)

Figure 4: Read cycle (Intel Mode)

OPERATING REQUIREMENTS: µC Interface, INTEL mode

Operating conditions: CFGSPI = 0, INT_NMOT = 1

VDD = 3 ... 5.5V, Ta = -25 ... 85 °C; input levels lo = 0 ... 0.45 V, hi = 2.4 V ... VDD

Item

Symbol

Parameter

Conditions

Fig.

Unit

Min.

Max.

I01

Setup Time:

Address stable before ALE hi

6lo

3/4

15

ns

I02

Signal Duration:

ALE at high level

3/4

10

ns

I03

Setup Time:

NCS hi

6lo until ALE hi6lo

3/4

10

ns

l04

Hold Time:

Address stable after ALE hi

6lo

3/4

15

ns

l05

Setup Time:

ALE hi

6lo until NWR_E hi6lo

30

ns

l06

Signal Duration:

NWR_E at low level

310

ns

l07

Setup Time:

Data stable before NWR_E lo

6hi

315

ns

l08

Hold Time:

Data stable after NWR_E lo

6hi

30

ns

l09

Hold Time:

NCS lo after NWR_E lo

6hi

30

ns

l10

Hold Time:

ALE lo after NWR_E lo

6hi

NCS = lo

3/4

15

ns

l11

Setup Time:

ALE hi

6lo until NRD_RNW hi6lo

40

ns

l12

Signal Duration:

NRD_RNW at low level

470

ns

l13

Propagation Delay:

Data stable after NRD_RNW hi

6lo

4

0

25

ns

l14

Propagation Delay:

Data Bus high impedance after

NRD_RNW lo

6hi

4

0

25

ns