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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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STM8L15 Datasheet(PDF) 105 Page - STMicroelectronics |
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STM8L15 Datasheet(HTML) 105 Page - STMicroelectronics |
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105 / 122 page  STM8L151xx, STM8L152xx Electrical parameters Doc ID 15962 Rev 5 105/122 Figure 38. ADC1 accuracy characteristics Figure 39. Typical connection diagram using the ADC 1. Refer to Table 51 for the values of RAIN and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 40 or Figure 41, depending on whether VREF+ is connected to VDDA or not. Good quality ceramic 10 nF capacitors should be used. They should be placed as close as possible to the chip. EO EG 1LSBIDEAL (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. 4095 4094 4093 5 4 3 2 1 0 7 6 1 2 3 456 7 4093 4094 4095 4096 (1) (2) ET ED EL (3) VDDA VSSA ai14395b VREF+ 4096 (or depending on package)] VDDA 4096 [1LSBIDEAL = |
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