ISL89367

3

FN7727.0

January 31, 2011

Pin Configurations

ISL89367

(16 LD TDFN, EPSOIC)

TOP VIEW

EPAD

INVA

IN1A

INVB

IN2B

IN1B

IN2A

FDELB

RDELB

VSS

OUTB

OUTA

VDD

RDELA

FDELA

1

2

3

4

5

6

7

8

12

9

10

11

13

14

15

16

VREF+

VREF-

INVx

IN1x

IN2x

OUTx

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

1

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

0

OUTx

IN1x

IN2x

INVx

TRUTH TABLE

Pin Descriptions

PIN

NUMBER SYMBOL

DESCRIPTION

1, 8

VREF+

VREF-

VREF+ and VREF- are the reference voltages for

the IN1A, IN1B, IN2A, and IN2B logic inputs.

VREF+ is normally connected to the positive bias

voltage of the input logic. VREF- is normally

connected to the ground reference of the input

logic.

2, 7

INVA or

INVB

Connect these pins to VDD to invert the

corresponding output. Connect to VSS to not

invert the corresponding output.

3, 4,

5, 6

IN1A,

IN2A,

IN1B,

IN2B

ANDed logical inputs. One input to each channel

can be used as an enable. Logic high threshold is

63% of [(VREF+) - (VREF-)]. Logic low threshold is

37% of [(VREF+) - (VREF-)].

9, 16

FDELB,

FDELA

Connect a resistor between these pins and VSS to

program the duration of the falling edge

propagation delay of the corresponding output

relative to the logic inputs.

10, 15

RDELB,

RDELA

Connect a resistor between these pins and VSS to

program the duration of the rising edge

propagation delay of the corresponding output

relative to the logic inputs.

11, 14

VSS, VDD Output bias voltage. (VDD to VSS) range is 4.5V to

16V. VSS may be negative relative to VREF-.

12, 13

OUTB,

OUTA

6A peak outputs. Output voltage swing is

between VDD and VSS.

EPAD

Must be connected to logic ground (VREF-).

Ordering Information

PART NUMBER

(Notes 1, 2, 3)

PART MARKING

TEMP RANGE

(°C)

INPUT CONFIGURATION

PACKAGE

(Pb-Free)

PKG.

DWG. #

ISL89367FRTAZ

367A

-40 to +125

non-inverting

16 Ld 3x5 TDFN

L16.5x3

NOTES:

1. Add “-T”, suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL89367.For more information on MSL, please see Technical Brief

TB363.