ISL89367

9

FN7727.0

January 31, 2011

Functional Description

Note: In the following discussion, when a lower case “n” or “x” is

used in a pin name, the “n” can be replaced by “1” or “2” and “x”

can be replaced by “A” or “B”.

The ISL89367 drivers are designed specifically for Synchronous

Rectifier (SR) applications but can also be used for any MOSFET

driver application especially when a precision propagation time

delay is required for the output rising for falling edge (or both).

To prevent unexpected glitches on the output of the ISL89367

during the application or removal of bias voltage, the

undervoltage (UV) lock-out holds the outputs of the driver low

when VDD < ~3.3 VDC regardless of the input logic level.

The fast rising (or falling) output drive current of the ISL89367

minimizes the turn-on (or off) delay due to the input capacitance

of the driven FET. The switching transition period at the Miller

plateau is also minimized by the high amplitude drive currents.

(See the specified Miller plateau currents in the AC Electrical

Specifications on page 6).

Input Logic Voltage Levels

The input logic (INnx) has thresholds of 37% (falling input) and

thresholds.

Programmable Delays

The propagation time delays are programmed by resistors

connected between RDELx or FDELx and VSS. A resistor

connected to RDELx delays the rising edge of OUTx. Likewise, a

resistor connected to FDELx delays the falling edge of OUTx. The

resistors should be connected as close as possible to the pins to

prevent noise coupling into these connections. In extremely noisy

applications, it may be necessary to bypass the resistors with a

0.01µF or smaller decoupling capacitor. The time delay varies

linearly between ~40ns and ~265ns for values from 2k

Ω to

20k

Ω. If no time delay is required, short RDELx and FDELx to

VSS. Programmed delays for resistor values < 2k are not

specified or recommended. Resistor values > 20k are also not

recommended.

Delays Greater than 270ns

For application requiring delay durations longer than 270ns, the

ISL89367 also offers a solution. The input logic pins have

precision thresholds which are designed for precision time delays

of either the rising of falling edge of OUTx by using the time

constant of a resistor and capacitor. The logic inputs pins of the

driver, INnx, are connected to the positive inputs of the input

comparators. The positive and negative transition threshold

voltages are established on the negative inputs of these

the threshold transitions are proportional to the bias voltage of

the input logic. Consequently, the time delays are independent of

the accuracy of the input logic bias voltage.

Figure 16 illustrates a circuit that is used to delay the rising edge

of OUTA relative to the rising edge of the signal source. The value

of C should also be substantially larger than the input

capacitance of the input pin of the ISL89367, the parasitic

capacitance associated with the traces, and the output

CMOS.

The calculation of the rising delay is simply shown by Equation 1:

This is a consequence of the 37%/63% thresholds.

FIGURE 15. PROGRAMMABLE DELAY vs RDEL and FDEL

0

50

100

150

200

250

300

350

0

5

10

15

20

RDT (2k to 20k)

-40°C (WORST CASE)

+25°C (TYPICAL)

+125°C (WORST CASE)

×

=

(EQ. 1)