SC1406GCTSTR datasheet(18/28 Pages) SEMTECH

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ã 2000 Semtech Corp.

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POWER MANAGEMENT

SC1406G

Soft-Start Design:

The three outputs have two soft-start controls, with the two

linear regulators sharing one of them. The soft-start timing is

controlled with a capacitor charged by a nominal 1mA current

source. The soft-start period is the time to charge the soft-start

capacitors to Vref (though the voltage eventually terminates

near Vcc). The soft-start capacitor value is calculated for a 2ms

nominal time by:

The soft-start period for V

CORE should be somewhat longer due to

the higher power and larger amount of output capacitance to

charge. Choosing 3ms results in C10=1800pF.

Low Battery Design:

The SC1406G provides a low-battery indication with a hysteresis

current feature. That is, when the voltage at the LBIN pin is

above the reference, the input bias current is very low. Once the

threshold (a 1.225V bandgap) is reached and LBIN trips, a

0.6mA to 10mA current source must be overcome by the

battery and divider before the converter is allowed to come on

again. For the sample converter, assume V

TRIP = 9.5V. Ignoring

bias currents, and assuming R8=20kW.

In the example schematic, R9 = 43kW to accommodate

operation down to 4.5VDC. The rounded value gives a V

TRIPLO of

9.62V. In order for LBIN to reset, the current source must be

overpowered, so:

The hysteresis current, in this case provides a voltage hysteresis

of 0.82V to 1.38V.

C10 provides noise filtering at the LBIN input. The 1nF value is

intended to provide attenuation at the lowest frequency load of

the battery. To disable this feature, tie LBIN (pin 17) to Vcc of

the SC1406 through a resistor (10kW is a good nominal value).

Clamp Design:

The clamp circuit is an open-collector uni-directional level shifter

capable of driving a 16mA load with a 5ns typical delay time.

VCIN (pin 4) must be referenced to the V

IO rail; VCOUT (pin 3)

can be tied to either V

CLK or VCC , depending on the connection of

the pull-up resistor. The clamp circuit has a dedicated refer-

ence, VCBYP (pin 5) that requires a 1.5nF capacitor for proper

operation. The clamp circuit is not normally used in Pentium III

mobile computers. To disable this function, tie VCIN to analog

ground, with VCOUT and VCBYP open.

Other Features and Functions:

ENABLE is a 5V-safe CMOS input with an upper threshold

voltage at 70% of Vcc and a lower threshold of 0.8V. It can be

used in two different ways. One is to tie ENABLE to the PWRDY

pin of the SC1405; this will bring both the SC1405 and SC1406

up properly even if ENABLE can be active before the system 5V

supply is stable. Alternately, the ENABLE lines of both devices

can be tied together.

CO is the clock output from the SC1406 to the SC1405.

POWERGOOD is LO (inactive) whenever any of the following

conditions is present:

1 Vcore is more than 10% higher or lower than its set-

point,

2 Either soft-start pin is lower than its threshold

3 Vcc is below the UVLO threshold

4 LBIN is active

POWERGOOD is HI (active) when none of the above is true, as

during normal operating conditions.

SC1405 Design Example:

The main function of SC1405 is to rapidly drive the power

MOSFETs on and off on using a break before make algorithm

to prevent cross conduction in the FETs.

FET selection:

The duty cycle (d) of the converter is a function of the input

voltage. In most applications, where the converter runs directly

from the battery, AC adapter, or even a regulated +5V source, d

is always going to be much less than 50%. The low-side (or

synchronous) FET, therefore, is conducting most of the time;

further, because the diode clamps the voltage across the low-

side FET, it switches with virtually zero voltage across it. The

high-side (or control) FET conducts for a relatively small amount

of time, but has to switch the entire voltage. Therefore, the

control FET can have a relatively high R

DS (ON), but needs to have

low capacitive losses, and the synchronous FET needs to have a

low R

DS (ON), and can have higher capacitance. To accomplish

this, one can use a single FET type, with two or more in parallel

in the low-side, or one can use FET sets with individually

optimized devices.

CSS

ICSS tSS

⋅

VREF

CSS

1.176

−

VLBTRIP

VLBREF

⋅

VTRIPHIMAX VLBREF

µA

⋅

VLBREF











⋅

VTRIPHIMAX 10.986 V

V TRIPHIMIN

V LBREF

µA

⋅

V LBREF











⋅

VTRIPHIMIN 10.438V

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