SC1406GCTSTR datasheet(19/28 Pages) SEMTECH

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POWER MANAGEMENT

SC1406G

The current in the control FET is approximately:

This current also should be used to size input capacitors; the

three input capacitors need a ripple current rating of 1.8A each,

to meet this requirement. The synchronous FET should be sized

for the full output current. Since the drive is derived from 5V,

both FETs should be sized using R

DS(ON) and current ratings for

Vgs=4.5V.

Gate resistors are always recommended, and are required for

the control FET and for multiple synchronous FETs (one resistor

per gate). The value is dependent on FET selection and layout.

Generally, start with 2.2W to 4.7W for R11 -13 to evaluate the

circuit for EMI performance and Miller (gate to drain) capaci-

tance effects. Increasing the high-side FET gate resistor value

will lessen both problems, but at the expense of higher switch-

ing losses.

Miller capacitance in the low-side FET can cause it to turn ON as

the high-side FET turns on. It acts as a charge-pump capacitor to

couple the current from the fast dV/dt on the drain into the gate.

The voltage that appears on the low-side FET gate is:

If the voltage is sufficient to conduct significant current, then

efficiency is poor, and in extreme cases, the devices can be

damaged. For a given FET, Cgs is fixed, so one possible solution

is to slow down dV/dt; another is to reduce Zdrive. Reducing

Zdrive is primarily a function of layout and FET selection, since

the internal Rg of the FET can be on the order of 10W. The

SC1405 driver is typically 1W; so, given the short (10-20ns) dt,

Zdrive can be dominated by trace inductance. For long gate

drive traces, this inductance can resonate with the gate capaci-

tance; in this case, a few ohms of gate resistance can damp the

circuit and actually reduce the peak gate voltage. However, the

best practice is to locate the SC1405 as near as possible to the

low-side FET and run wide traces to the gate.

Other potential solutions are to choose FETs with a low Cds/Cgs

ratio, low Rg, or add a capacitor from the low-side gate drive to

ground to externally lower the Cds/Cgs ratio.

Charge Pump Design:

The high-side drive circuit is tied to the source of the FET at DRN

(pin 12) and rides along the switching (phase) node rather than

being hard referenced to ground. The drive circuit makes use of

this switching action to pump charge from the 5V source up to

the BST pin (pin 14) to drive the control FET. When Q4 and Q5

are ON, C17 is charged through D1 to nearly 5V; when Q4 and

Q5 turn off, this voltage is available to turn Q3 on. C17 rides

along with the source, maintaining the drive level.

The charge pump capacitor needs to be low impedance, with a

value at least 100 times the gate capacitance it has to charge.

Ceramic capacitors are recommended. Schottky diodes are

recommended for D1. Wide traces are also required for the

charge pump traces.

In very low power situations, the low side drive may be disabled

via use of the SMOD pin (pin 5). This pin effectively prevents

reverse current from flowing in the inductor, so the inductor

current becomes discontinuous and the operating frequency is

reduced. The reduced losses related to circulating current and

faster switching need to be compared with the additional loss in

using the diode rather than the synchronous rectifier to deter-

mine whether it improves low load efficiency in the system

application. In addition, the system must supply the SMOD

signal at the appropriate time.

Phase Node Design:

The phase node is one of the most critical nodes in the con-

verter design, and must be treated with care. When neither Q3

nor Q4 is on, the inductor current flows through D2. D2 should

be a Schottky diode with a forward voltage at the peak inductor

current less than the forward voltage of the parasitic diode of

the FET, to keep it from conducting, and improving efficiency.

Holding the gate of Q4 low until the phase node reaches 1V for

a high to low transition provides shoot-through protection. For a

low to high transition, the high-side driver is held off by an

internal 20ns delay. This period may be extended using C15,

connected to pin 6, to provide an additional delay of approxi-

mately 1ns/pF. Size C15 to provide dead time for the worst-

case drive conditions given the choice of control FET and gate

drive resistor.

The phase node voltage at DRN (pin 12) must not go below -2V;

very short (<25nS) pulses to -5V can be tolerated. Excessive

negative transients may result in double pulsing of the gate

drive, and in severe cases, device damage.

The phase node, since it switches at very high rates of speed, is

generally the largest source of common-mode noise in the

converter circuit. For this reason, it should be kept to a

minimum size consistent with its connectivity and current

carrying requirements. Occasionally, a snubber network (R17/

C18) is required to dampen parasitic ringing on the phase node

caused by parasitic inductance and capacitance excited by the

switching. One approach to snubber design is to record the

frequency and amplitude of ringing before the snubber, then add

pure capacitance until the frequency is reduced, then adding

resistance until the required damping is achieved.

IQ3RMS

ICC650MAX

dMAX

⋅

IQ3RMS 5.44 A

ZDRIVE

CDS

CGS

⋅

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