ATSAM3S2BA-MU datasheet(28/64 Pages) ATMEL

28 / 64 page

6500CS–ATARM–24-Jan-11

SAM3S Summary

7.5

Master to Slave Access

All the Masters can normally access all the Slaves. However, some paths do not make sense,

for example allowing access from the Cortex-M3 S Bus to the Internal ROM. Thus, these paths

are forbidden or simply not wired and shown as “-” in the following table.

7.6

Peripheral DMA Controller

• Handles data transfer between peripherals and memories

• Low bus arbitration overhead

– One Master Clock cycle needed for a transfer from memory to peripheral

– Two Master Clock cycles needed for a transfer from peripheral to memory

• Next Pointer management for reducing interrupt latency requirement

The Peripheral DMA Controller handles transfer requests from the channel according to the fol-

lowing priorities (Low to High priorities):

Table 7-3.

SAM3S Master to Slave Access

Masters

Slaves

Cortex-M3 I/D

Bus

Cortex-M3 S

Bus

PDC

CRCCU

Internal SRAM

Internal ROM

Internal Flash

External Bus Interface

Peripheral Bridge

Table 7-4.

Peripheral DMA Controller

Instance Name

Channel T/R

100 & 64 Pins

48 Pins

PWM

Transmit

TWI1

Transmit

TWI0

Transmit

UART1

Transmit

UART0

Transmit

USART1

Transmit

N/A

USART0

Transmit

DAC

Transmit

N/A

SPI

Transmit

SSC

Transmit

HSMCI

Transmit

N/A

PIOA

Transmit

TWI1

Receive

TWI0

Receive

UART1

Receive

N/A

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