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MMA8653FC Datasheet(PDF) 21 Page - Freescale Semiconductor, Inc |
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MMA8653FC Datasheet(HTML) 21 Page - Freescale Semiconductor, Inc |
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21 / 56 page  MMA8653FC Sensors Freescale Semiconductor, Inc. 21 6.2 Register bit map Note: Bits showing “—” can read as either 0 or 1, and these bits have no definition. Reg Field Definition Typ e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 STATUS Data Status R ZYXOW ZOW YOW XOW ZYXDR ZDR YDR XDR 01 OUT_X_MSB 10-bit X Data R XD9 XD8 XD7 XD6 XD5 XD4 XD3 XD2 02 OUT_X_LSB 10-bit X Data R XD1 XD0 0 0 0 0 0 0 03 OUT_Y_MSB 10-bit Y Data R YD9 YD8 YD7 YD6 YD5 YD4 YD3 YD2 04 OUT_Y_LSB 10-bit Y Data R YD1 YD0 0 0 0 0 0 0 05 OUT_Z_MSB 10-bit Z Data R ZD9 ZD8 ZD7 ZD6 ZD5 ZD4 ZD3 ZD2 06 OUT_Z_LSB 10-bit Z Data R ZD1 ZD0 0 0 0 0 0 0 07– 0A Reserved — R 0 0 0 0 0 0 0 0 0B SYSMOD System Mode R 0 0 0 0 0 0 SYSMOD1 SYSMOD0 0C INT_SOURCE Interrupt Status R SRC_ASLP 0 0 SRC_LNDPRT 0 SRC_FF_MT 0 SRC_DRDY 0D WHO_AM_I ID Register R 0 1 0 1 1 0 1 0 0E XYZ_DATA_CFG Data Config R/ W 00 0 0 0 0 FS1 FS0 0F Reserved — R — — — — — — — — 10 PL_STATUS Portrait Landscape Status R NEWLP LO 0 0 0 LAPO[1] LAPO[0] BAFRO 11 PL_CFG Portrait Landscape Configuration R/ W DBCNTM PL_EN 0 0 0 0 0 0 12 PL_COUNT Portrait Landscape Debounce R/ W DBNCE[7] DBNCE[6] DBNCE[5] DBNCE[4] DBNCE[3] DBNCE[2] DBNCE[1] DBNCE[0] 13 PL_BF_ZCOMP Portrait Landscape Back/Front Z Comp R0 1 0 0 0 1 0 0 14 PL_THS_REG Portrait Landscape Threshold R1 0 0 0 0 1 0 0 15 FF_MT_CFG Freefall/Motion Config R/ W ELE OAE ZEFE YEFE XEFE 0 0 0 16 FF_MT_SRC Freefall/Motion Status R EA 0 ZHE ZHP YHE YHP XHE XHP 17 FF_MT_THS Freefall/Motion Threshold R/ W DBCNTM THS6 THS5 THS4 THS3 THS2 THS1 THS0 18 FF_MT_COUNT Freefall/Motion Debounce R/ W D7 D6 D5 D4 D3 D2 D1 D0 19– 28 Reserved — R — — — — — — — — 29 ASLP_Count Counter setting for Auto-SLEEP/WAKE R/ W D7 D6 D5 D4 D3 D2 D1 D0 2A CTRL_REG1 Control Reg1 R/ W ASLP_RATE1 ASLP_RATE0 DR2 DR1 DR0 0 F_READ ACTIVE 2B CTRL_REG2 Control Reg2 R/ W ST RST — SMODS1 SMODS0 SLPE MODS1 MODS0 2C CTRL_REG3 Control Reg3 R/ W — — WAKE_LNDPRT — WAKE_FF_MT 0 IPOL PP_OD 2D CTRL_REG4 Control Reg4 R/ W INT_EN_ASLP — — INT_EN_LNDPRT — INT_EN_FF_MT 0 INT_EN_DRDY 2E CTRL_REG5 Control Reg5 R/ W INT_CFG_ASLP — — INT_CFG_LNDPRT — INT_CFG_FF_MT 0 INT_CFG_DRD Y 2F OFF_X X 8-bit offset R/ W D7 D6 D5 D4 D3 D2 D1 D0 30 OFF_Y Y 8-bit offset R/ W D7 D6 D5 D4 D3 D2 D1 D0 31 OFF_Z Z 8-bit offset R/ W D7 D6 D5 D4 D3 D2 D1 D0 |
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