MMA8653FC datasheet(39/56 Pages) FREESCALE

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MMA8653FC

Sensors

Freescale Semiconductor, Inc.

6.7

Auto-WAKE/SLEEP Detection

6.7.1

0x29: ASLP_COUNT, Auto-WAKE/SLEEP Detection Register (Read/Write)

The ASLP_COUNT register sets the minimum time period of inactivity required to change the current ODR value, from the value

specified in the DR[2:0] register to ASLP_RATE register value, provided that the SLPE bit is set to a logic ‘1’ in the CTRL_REG2

register. See Table 30, “ASLP_COUNT Relationship with ODR" for functional blocks that may be monitored for inactivity in order

to trigger the “return to SLEEP” event.

Figure 37. 0x29: ASLP_COUNT Auto-WAKE/SLEEP Detection Register (Read/Write)

D7-D0 defines the minimum duration time to change current ODR value from DR to ASLP_RATE. Time step and maximum value

depend on the ODR chosen as shown in Table 30, “ASLP_COUNT Relationship with ODR".

In order to wake the device, the desired functions must be enabled in CTRL_REG4 and set to WAKE from SLEEP in

CTRL_REG3. All enabled functions will still function in SLEEP mode at the SLEEP ODR. Only the functions that have been

selected for WAKE from SLEEP will WAKE the device.

MMA8653FC has 2 functions that can be used to keep the sensor from falling asleep namely, Orientation, and Motion/Freefall.

One or more of these functions can be enabled. To WAKE the device, 2 functions are provided : Orientation, and the Motion/

Freefall. The Auto-WAKE/SLEEP interrupt does not affect the WAKE/SLEEP, nor does the data ready interrupt.

If the Auto-SLEEP bit is disabled, then the device can only toggle between STANDBY and WAKE mode. If Auto-SLEEP interrupt

is enabled, transitioning from ACTIVE mode to Auto-SLEEP mode and vice versa generates an interrupt.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Table 29. ASLP_COUNT register

Field

Description

D[7:0]

Duration value. Default value: 0000_0000.

Table 30. ASLP_COUNT Relationship with ODR

Output Data Rate

(ODR)

Duration

ODR Time

Step

ASLP_COUNT

Step

800 Hz

0 to 81s

1.25 ms

320 ms

400 Hz

0 to 81s

2.5 ms

320 ms

200 Hz

0 to 81s

5 ms

320 ms

100 Hz

0 to 81s

10 ms

320 ms

50 Hz

0 to 81s

20 ms

320 ms

12.5 Hz

0 to 81s

80 ms

320 ms

6.25 Hz

0 to 81s

160 ms

320 ms

1.56 Hz

0 to 162s

640 ms

Table 31. SLEEP/WAKE Mode Gates and Triggers

Interrupt Source

Event restarts timer and

delays Return to SLEEP

Event will WAKE from SLEEP

SRC_LNDPRT

Yes

SRC_FF_MT

Yes

SRC_ASLP

SRC_DRDY

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