WM8740

Production Data

w

PD, Rev 4.4, April 2010

9

INTERNAL POWER ON RESET CIRCUIT

Power On Reset

Circuit

10K

10K

Figure 4 Internal Power On Reset Circuit Schematic

The WM8740 includes an internal Power On Reset Circuit which is used reset the digital logic into a

default state after power up.

Figure 4 shows a schematic of the internal POR circuit. The POR circuit is powered from AVDD. The

circuit monitors DVDD and VMIDL and asserts PORB low if DVDD or VMIDL are below the minimum

On power up, the POR circuit requires AVDD to be present to operate. PORB is asserted low until

AVDD and DVDD and VMIDL are established. When AVDD, DVDD, and VMIDL have been

established, PORB is released high, all registers are in their default state and writes to the digital

interface may take place.

On power down, PORB is asserted low whenever DVDD or VMIDLL drop below the minimum

If AVDD is removed at any time, the internal Power On Reset circuit is powered down and PORB will

follow AVDD.

In most applications the time required for the device to release PORB high will be determined by the

charge time of the VMIDLL node.

Figure 5 Typical Power Up Sequence where DVDD is Powered before AVDD