RT9108NL datasheet(10/13 Pages) RICHTEK

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RT9108NL

DS9108NL-01

June 2012

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Application Information

Amplifier Gain Setting

The gain of the RT9108NL amplifier can be set by two

input terminals, GAIN0 and GAIN1, shown as Table 1.

The gain setting is realized by changing the taps on the

input resistors and feedback resistors inside the amplifier.

This causes the input impedance (Z

I) to be dependent on

the gain setting. The actual gain settings are controlled

by the ratios of the resistors, so the gain variation from

part-to-part is small. However, the input impedance from

part-to-part at the same gain may shift by ±20% due to

shifts in the actual resistance of the input resistor.

Amplifier

GAIN (dB)

Input Impedance

(

Ω)

GAIN1

GAIN0

Typ

100k

50k

25k

12.5k

Table 1. Gain Setting

()

PVCC

Output Power =

Width_Factor

R1.35

PLIMIT Voltage (V)

Width_Factor

4.6 (GVDD)

2.7 to 2.9

0.765

2.3 to 2.5

0.578

1.9 to 2.1

0.410

1.6 to 1.7

0.265

1.2 to 1.3

0.149

Table 2. PLIMIT Width Limit

PVCC = 12V,

VIN = 1.5VRMS ,RL=8Ω

Gain = 20dB

Gain = 26dB

Gain = 32dB

Gain = 36dB

PLIMIT Voltage (V)

Output Power (W)

4.6 (GVDD)

11.6

13.3

14.3

2.7 to 2.9

9.13

10.2

10.7

10.8

2.3 to 2.5

7.01

7.67

7.95

8.2

1.9 to 2.1

5.07

5.36

5.47

5.6

1.6 to 1.7

3.36

3.43

3.55

3.6

1.2 to 1.3

1.95

1.97

1.98

Table 3. Typical PLIMIT Operation at 12V Power Supply

For the best power off pop performance, tarn off the

amplifier in the shutdown mode prior to removing the power

supply voltage.

GVDD Supply

The GVDD Supply is used to supply the gate drivers for

the output full bridge transistors. Connect a 1

μF capacitor

from this pin to ground. The typical GVDD output voltage

is 4.6V.

Power LIMIT

The voltage at pin 10 can used to limit the power to levels

below the supply rail. Add a resistor divider from GVDD to

ground to set the voltage at the PLIMLT pin. An external

reference may also be used if tighter tolerance is required.

Also add a 1

μF capacitor from pin 10 to ground.

There are five steps to sets a limit on the output peak-to-

peak voltage. The limiting is done by limiting the duty

cycle to fixed maximum value. PLIMIT pin directly connect

to GVDD for no power limit.

SD Operation

The RT9108NL employs a shutdown mode operation

designed to reduce supply current (ICC) to the absolute

minimum level for power saring. The SD input terminal

should be held high (see specification table for trip point)

in normal operation. Pulling SD low causes the outputs

to mute and the amplifier to enter a low current state.

Leaving SD floating will cause the, amplifier operation to

be unpredictable. Never leave SD pin unconnected!

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