AD7013ARS datasheet(6/20 Pages) AD

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–6–

REV. A

AD7013

Limit at

Parameter

A = –40°C to +85°C

Units

Description

160

ns min

MCLK Cycle Time

ns min

MCLK High Time

ns min

MCLK Low Time

ns min

MCLK Rising Edge to DxCLK Rising Edge Propagation Delay

ns max

DxCLK Cycle Time

1–20

ns min

DxCLK Minimum High Time

1–20

ns min

DxCLK Minimum Low Time

ns min

DxCLK Rising Edge to FRAME IN Setup Time

ns min

DxCLK Rising Edge to FRAME IN Hold Time

16t

ns min

FRAME IN Cycle Time

ns min

DxCLK Rising Edge to DATA IN Setup Time

ns min

DxCLK Rising Edge to DATA IN Hold Time

ns min

FRAME IN Rising Edge to FRAME OUT Rising Edge Propagation Delay

ns max

MODE1 Low to FRAME OUT 3-STATE

ns max

MODE1 High to FRAME OUT Active

NOTE

14 is derived from the measured time taken by the FRAME OUT pin to change 0.5 V when loaded with the circuit of Figure 1.

The measured number is then

extrapolated back to remove the effects of charging or discharging the 80 pF capacitor. This means that the time quoted in the Timing Characteristics is the

AA = +5 V ± 10%; VDD = +5 V ± 10%; AGND = DGND =0 V,

MCLK = 6.2208 MHz; TA = TMIN to TMAX, unless otherwise noted)

CONTROL SERIAL INTERFACE TIMING1

MxCLK (I)

DxCLK (O)

DATA IN (I)

NOTE: (O) INDICATES AN OUTPUT, (I) INDICATES AN INPUT, MODE1 = LOGIC HIGH

MODE1 (I)

FRAME OUT (O)

FRAME IN (I)

DATA

DB9

DB8

DB1

DB0

ADDRESS

IGNORED

3 – STATE

Figure 2. 16-Bit Serial Interface for Writing to the AD7013 Internal Registers

1.6mA

IOL

50pF

TO OUTPUT PIN

+2.1V

IOH

200

µA

Figure 1. Load Circuit for Digital Outputs

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